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1 tms320dm6431 digital media processor 1.1 features tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 high-performance digital media processor c64x+ l1/l2 memory architecture (dm6431) ? 256k-bit (32k-byte) l1p program ? 3.33-ns instruction cycle time ram/cache [flexible allocation] ? 300-mhz c64x+? clock rate ? 512k-bit (64k-byte) l1d data ram/cache [flexible allocation] ? eight 32-bit c64x+ instructions/cycle ? 512k-bit (64k-byte) l2 unified mapped ? 2400 mips ram/cache [flexible allocation] ? fully software-compatible with c64x supports little endian mode only ? commercial and automotive (q or s suffix) grades video processing subsystem (vpss), vpfe only velociti.2? extensions to velociti? ? front end provides: advanced very-long-instruction-word (vliw) tms320c64x+? dsp core ccd and cmos imager interface ? eight highly independent functional units bt.601/bt.656 digital ycbcr 4:2:2 with velociti.2 extensions: (10-bit) interface six alus (32-/40-bit), each supports glueless interface to common video single 32-bit, dual 16-bit, or quad 8-bit decoders arithmetic per clock cycle external memory interfaces (emifs) two multipliers support four 16 x 16-bit ? 16-bit ddr2 sdram memory controller multiplies (32-bit results) per clock with 128m-byte address space (1.8-v i/o) cycle or eight 8 x 8-bit multiplies (16-bit supports up to 266-mhz (data rate) bus results) per clock cycle and interfaces to ddr2-400 sdram ? load-store architecture with non-aligned ? asynchronous 8-bit wide emif (emifa) support with up to 64m-byte address reach ? 64 32-bit general-purpose registers flash memory interfaces ? instruction packing reduces code size ? nor (8-bit-wide data) ? all instructions conditional ? nand (8-bit-wide data) ? additional c64x+? enhancements enhanced direct-memory-access (edma) protected mode operation controller (64 independent channels) exceptions support for error detection two 64-bit general-purpose timers (each and program redirection configurable as two 32-bit timers) hardware support for modulo loop one 64-bit watch dog timer auto-focus module operation one uart with rts and cts flow control c64x+ instruction set features ? byte-addressable (8-/16-/32-/64-bit data) master/slave inter-integrated circuit (i 2 c ? 8-bit overflow protection bus?) ? bit-field extract, set, clear one multichannel buffered serial port ? normalization, saturation, bit-counting (mcbsp0) ? velociti.2 increased orthogonality ? i2s and tdm ? c64x+ extensions ? ac97 audio codec interface compact 16-bit instructions ? spi additional instructions to support ? standard voice codec interface (aic12) complex multiplies ? telecom interfaces ? st-bus, h-100 ? 128 channel mode multichannel audio serial port (mcasp0) ? four serializers and spdif (dit) mode please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this document. all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2006?2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
1.2 description tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com high-end can controller (hecc) (multiplexed with other device functions) 10/100 mb/s ethernet mac (emac) packages: ? ieee 802.3 compliant ? 361-pin pb-free pbga package (zwt suffix), 0.8-mm ball pitch ? supports media independent interface (mii) ? 376-pin plastic bga package ? management data i/o (mdio) module (zdu suffix), 1.0-mm ball pitch three pulse width modulator (pwm) outputs 0.09- m m/6-level cu metal process (cmos) on-chip rom bootloader 3.3-v and 1.8-v i/o, 1.2-v internal (-3/-3q/-3s) individual power-savings modes applications: flexible pll clock generators ? digital media ieee-1149.1 (jtag?) ? networked media encode boundary-scan-compatible ? video imaging up to 111 general-purpose i/o (gpio) pins the tms320c64x+? dsps (including the tms320dm6431 device) are the highest-performance fixed-point dsp generation in the tms320c6000? dsp platform. the dm6431 device is based on the third-generation high-performance, advanced velociti? very-long-instruction-word (vliw) architecture developed by texas instruments (ti), making these dsps an excellent choice for digital media applications. the c64x+? devices are upward code-compatible from previous devices that are part of the c6000? dsp platform. the c64x? dsps support added functionality and have an expanded instruction set from previous devices. any reference to the c64x dsp or c64x cpu also applies, unless otherwise noted, to the c64x+ dsp and c64x+ cpu, respectively. with performance of up to 2400 million instructions per second (mips) at a clock rate of 300 mhz, the c64x+ core offers solutions to high-performance dsp programming challenges. the dsp core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. the c64x+ dsp core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic logic units (alus). the eight functional units include instructions to accelerate the performance in video and imaging applications. the dsp core can produce four 16-bit multiply-accumulates (macs) per cycle for a total of 1200 million macs per second (mmacs), or eight 8-bit macs per cycle for a total of 2400 mmacs. for more details on the c64x+ dsp, see the tms320c64x/c64x+ dsp cpu and instruction set reference guide (literature number spru732 ). the dm6431 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other c6000 dsp platform devices. the dm6431 core uses a two-level cache-based architecture. the level 1 program memory/cache (l1p) consists of 32k-byte (kb) memory space that can be configured as mapped memory or direct mapped cache. the level 1 data/memory memory/cache (l1d) consists of a 64kb memory space that can be configured as mapped memory or 2-way set-associative cache. the level 2 memory/cache (l2) consists of a 64kb memory space that is shared between program and data space. l2 memory can be configured as mapped memory, cache, or a combination of both. 2 tms320dm6431 digital media processor submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the peripheral set includes: 1 configurable video port; a 10/100 mb/s ethernet mac (emac) with a management data input/output (mdio) module; an inter-integrated circuit (i2c) bus interface; a multichannel buffered serial port (mcbsp0); a multichannel audio serial port (mcasp0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 111-pins of general-purpose input/output (gpio) with programmable interrupt/event generation modes, multiplexed with other peripherals; 1 uart with hardware handshaking support; 3 pulse width modulator (pwm) peripherals; 1 high-end controller area network (can) controller [hecc]; and 2 glueless external memory interfaces: an asynchronous external memory interface (emifa) for slower memories/peripherals, and a higher speed synchronous memory interface for ddr2. the dm6431 device includes a video processing subsystem (vpss) with a video processing front-end (vpfe) input used for video capture. the video processing front-end (vpfe) is comprised of a ccd controller (ccdc). the ccdc is capable of interfacing to common video decoders, cmos sensors, and charge coupled devices (ccds). the ethernet media access controller (emac) provides an efficient interface between the dm6431 and the network. the dm6431 emac support both 10base-t and 100base-tx, or 10 mbits/second (mbps) and 100 mbps in either half- or full-duplex mode, with hardware flow control and quality of service (qos) support. the management data input/output (mdio) module continuously polls all 32 mdio addresses in order to enumerate all phy devices in the system. the i2c port allows dm6431 to easily control peripheral devices and/or communicate with host processors. the high-end controller area network (can) controller [hecc] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications. the rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. for details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. the dm6431 has a complete set of development tools. these include c compilers, a dsp assembly optimizer to simplify programming and scheduling, and a windows? debugger interface for visibility into source code execution. submit documentation feedback tms320dm6431 digital media processor 3
1.3 functional block diagram tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 1-1 shows the functional block diagram of the dm6431 device. figure 1-1. tms320dm6431 functional block diagram 4 tms320dm6431 digital media processor submit documentation feedback jt ag interface system control plls/clock generator input clock(s) power/sleep controller pin multiplexing dsp subsystem c64x+ dsp cpu 32 kb l1 pgm 64 kb l2 ram 32 kb l1 data bt .656, y/c,raw (bayer) video processing subsystem (vpss) ccd controller video interface front end switched central resource (scr) peripherals edma i 2 c hecc uart serial interfaces ddr2 mem ctlr (16b) async emif/ nand/ (8b) program/data storage watchdog timer pwm system general- purpose timer emac with mdio connectivity mcasp mcbsp osc boot rom 10b gpio
contents tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 ranges of supply voltage and operating 1 tms320dm6431 digital media processor ........... 1 temperature (unless otherwise noted) ........... 118 1.1 features .............................................. 1 6 peripheral information and electrical 1.2 description ............................................ 2 specifications ......................................... 119 1.3 functional block diagram ............................ 4 6.1 parameter information ............................. 119 revision history ............................................... 6 6.2 recommended clock and control signal transition 2 device overview ......................................... 7 behavior ............................................ 120 2.1 device characteristics ................................ 7 6.3 power supplies .................................... 121 2.2 cpu (dsp core) description ......................... 8 6.4 enhanced direct memory access (edma3) controller ........................................... 128 2.3 c64x+ cpu .......................................... 11 6.5 reset ............................................... 140 2.4 memory map summary ............................. 12 6.6 external clock input from mxi/clkin pin ........ 149 2.5 pin assignments .................................... 16 6.7 clock plls ......................................... 151 2.6 terminal functions .................................. 24 6.8 interrupts ........................................... 156 2.7 device support ...................................... 56 2.8 device and development-support tool 6.9 external memory interface (emif) ................. 159 nomenclature ....................................... 56 6.10 video processing sub-system (vpss) overview . 168 2.9 documentation support ............................. 58 6.11 universal asynchronous receiver/transmitter (uart) ............................................. 173 3 device configurations ................................. 59 6.12 inter-integrated circuit (i2c) ....................... 175 3.1 system module registers ........................... 59 6.13 multichannel buffered serial port (mcbsp) ........ 179 3.2 power considerations ............................... 60 6.14 multichannel audio serial port (mcasp0) 3.3 clock considerations ................................ 62 peripheral .......................................... 188 3.4 boot sequence ...................................... 63 6.15 high-end controller area network controller 3.5 configurations at reset ............................. 74 (hecc) ............................................. 196 3.6 configurations after reset .......................... 75 6.16 ethernet media access controller (emac) ........ 202 3.7 multiplexed pin configurations ...................... 79 6.17 management data input/output (mdio) .......... 209 3.8 device initialization sequence after reset ........ 111 6.18 timers .............................................. 210 3.9 debugging considerations ......................... 113 6.19 pulse width modulator (pwm) ..................... 213 4 system interconnect ................................. 114 6.20 general-purpose input/output (gpio) ............. 215 4.1 system interconnect block diagram ............... 114 6.21 ieee 1149.1 jtag ................................. 219 5 device operating conditions ....................... 116 7 mechanical data ....................................... 221 5.1 absolute maximum ratings over operating 7.1 thermal data for zwt ............................. 221 temperature range (unless otherwise noted) ... 116 7.1.1 thermal data for zdu ............................. 222 5.2 recommended operating conditions ............. 117 7.1.2 packaging information ............................. 222 5.3 electrical characteristics over recommended submit documentation feedback contents 5
revision history tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com note: page numbers for previous revisions may differ from page numbers in the current version. this data manual revision history highlights the technical changes made to the sprs342b device-specific data manual to make it an sprs342c revision. see additions/modifications/deletions global updated/changed signal name from " c_we" to "c_we" updated/changed signal name from "c_wen" to "c_we" section 2.6 table 2-17 , multichannel audio serial port (mcasp0) terminal functions: updated/changed afsr0/dr0/gp[100] pin description from "... frame synchronization afsx0..." to "...frame synchronization afsr0..." updated/changed afsx0/dx1/gp[107] pin description from "...frame synchronization afsr0..." to "...frame synchronization afsx0..." section 6.7.1 updated/changed sentence from "ti requires emi filter manufacturer murata..." to "ti recommends emi filter manufacturer murata..." 6 revision history submit documentation feedback
2 device overview 2.1 device characteristics tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-1 , provides an overview of the tms320dm6431 dsp. the tables show significant features of the dm6431 device, including the capacity of on-chip ram, the peripherals, the cpu frequency, and the package type with pin count. table 2-1. characteristics of the dm6431 processor hardware features dm6431 ddr2 memory controller (16-bit bus width) [1.8 v i/o] asynchronous (8-bit bus width), asynchronous emif [emifa] ram, flash, (8-bit nor or 8-bit nand) edma3 1 (64 independent channels, 8 qdma channels) 2 64-bit general purpose timers (configurable as 2 64-bit or 4 32-bit) 1 64-bit watch dog peripherals uart 1 (with rts and cts flow control) not all peripherals pins i2c 1 (master/slave) are available at the same time (for more detail, see mcbsp 1 the device configuration mcasp 1 (4 serailizers) section). 10/100 ethernet mac (emac) with 1 management data input/output (mdio) general-purpose input/output port (gpio) up to 111 pins pwm 3 outputs configurable video port 1 input (vpfe) hecc 1 size (bytes) 128kb ram, 64kb rom 32k-byte (32kb) l1 program (l1p) ram/cache (cache up to 32kb) on-chip memory organization 64kb l1 data (l1d) ram/cache 64kb unified mapped ram/cache (l2) 64kb boot rom revision id register (mm_revid.[15:0]) see the tms320dm6437/35/33/31 digital media megamodule rev id (address location: 0x0181 2000) processor (dmp) [silicon revisions 1.1 and 1.0] silicon errata (literature number sprz250 ). cpu id + cpu rev id control status register (csr.[31:16]) jtagid register see section 6.21.1 , jtag id (jtagid) register jtag bsdl_id (address location: 0x01c4 0028) description(s) cpu frequency mhz 300 cycle time ns 3.33 ns (-3/-3q/-3s) core (v) 1.2 v (-3/-3q/-3s) voltage i/o (v) 1.8 v, 3.3 v mxi/clkin frequency multiplier pll options x1 (bypass), x14 to x30 (27 mhz reference) 16 x 16 mm, 0.8 mm pitch 361-pin bga (zwt) bga package(s) 23 x 23 mm, 1.0 mm pitch 376-pin bga (zdu) process technology m m 0.09 m m product preview (pp), advance information (ai), product status (1) pd or production data (pd) (1) production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. submit documentation feedback device overview 7
2.2 cpu (dsp core) description tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the c64x+ central processing unit (cpu) consists of eight functional units, two register files, and two data paths as shown in figure 2-1 . the two general-purpose register files (a and b) each contain 32 32-bit registers for a total of 64 registers. the general-purpose registers can be used for data or can be data address pointers. the data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 lsbs of data placed in an even register and the remaining 8 or 32 msbs in the next upper register (which is always an odd-numbered register). the eight functional units (.m1, .l1, .d1, .s1, .m2, .l2, .d2, and .s2) are each capable of executing one instruction every clock cycle. the .m functional units perform all multiply operations. the .s and .l units perform a general set of arithmetic, logical, and branch functions. the .d units primarily load data from memory to the register file and store results from the register file into memory. the c64x+ cpu extends the performance of the c64x core through enhancements and new features. each c64x+ .m unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). there is also support for galois field multiplication for 8-bit and 32-bit data. many communications algorithms such as ffts and modems require complex multiplication. the complex multiply (cmpy) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. there are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. the 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types. the .l or (arithmetic logic unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. there are also saturated forms of these instructions. the c64x+ core enhances the .s unit in several ways. in the c64x core, dual 16-bit min2 and max2 comparisons were only available on the .l units. on the c64x+ core they are also available on the .s unit which increases the performance of algorithms that do searching and sorting. finally, to increase data packing and unpacking throughput, the .s unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. unpack instructions prepare 8-bit data for parallel 16-bit operations. pack instructions return parallel results to output precision including saturation support. other new features include: sploop - a small instruction buffer in the cpu that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. the sploop buffer reduces the code size associated with software pipelining. furthermore, loops in the sploop buffer are fully interruptible. compact instructions - the native instruction size for the c6000 devices is 32 bits. many common instructions such as mpy, and, or, add, and sub can be expressed as 16 bits if the c64x+ compiler can restrict the code to use certain registers in the register file. this compression is performed by the code generation tools. instruction set enhancement - as noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit galois field multiplication. exceptions handling - intended to aid the programmer in isolating bugs. the c64x+ cpu is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). privilege - defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. local memory is divided into multiple pages, each with read, write, and execute permissions. device overview 8 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 time-stamp counter - primarily targeted for real-time operating system (rtos) robustness, a free-running time-stamp counter is implemented in the cpu which is not sensitive to system stalls. for more details on the c64x+ cpu and its enhancements over the c64x architecture, see the following documents: tms320c64x/c64x+ dsp cpu and instruction set reference guide (literature number spru732 ) tms320c64x+ dsp megamodule reference guide (literature number spru871 ) tms320c64x to tms320c64x+ cpu migration guide application report (literature number spraa84 ) tms320c64x+ dsp cache user's guide (literature number spru862 ) submit documentation feedback device overview 9
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 2-1. tms320c64x+? cpu (dsp core) data paths device overview 10 submit documentation feedback src2 src2 .d1 .m1 .s1 .l1 long src odd dst src2 src1 src1src1 src1 even dsteven dst odd dst dst1 dst src2src2 src2 long src da1 st1bld1b ld1a st1a data path a odd register file a (a1, a3, a5...a31) odd register file b (b1, b3, b5...b31) .d2 src1 dst src2 da2 ld2a ld2b src2 .m2 src1 dst1 .s2 src1 even dst long src odd dst st2a st2b long src .l2 even dst odd dst src1 data path b control register 32 msb 32 lsb dst2 (a) 32 msb 32 lsb 2x1x 32 lsb 32 msb 32 lsb 32 msb dst2 (b) (b) (a) 8 8 8 8 32 32 32 32 (c) (c) even register file a (a0, a2, a4...a30) even register file b (b0, b2, b4...b30) (d) (d) (d) (d) a. on .m unit, dst2 is 32 msb. b. on .m unit, dst1 is 32 lsb. c. on c64x cpu .m unit, src2 is 32 bits; on c64x+ cpu .m unit, src2 is 64 bits. d. on .l and .s units, odd dst connects to odd register files and even dst connects to even register files.
2.3 c64x+ cpu tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the c64x+ core uses a two-level cache-based architecture. the level 1 program memory/cache (l1p) consists of 32 kb memory space that can be configured as mapped memory or direct mapped cache. the level 1 data memory/cache (l1d) consists of a 64 kb memory space that can be configured as mapped memory or 2-way set associated cache. the level 2 memory/cache (l2) consists of a 64 kb memory space that is shared between program and data space. l2 memory can be configured as mapped memory, cache, or a combination of both. table 2-2 shows a memory map of the c64x+ cpu cache registers for the device. table 2-2. c64x+ cache registers hex address range register acronym description 0x0184 0000 l2cfg l2 cache configuration register 0x0184 0020 l1pcfg l1p size cache configuration register 0x0184 0024 l1pcc l1p freeze mode cache configuration register 0x0184 0040 l1dcfg l1d size cache configuration register 0x0184 0044 l1dcc l1d freeze mode cache configuration register 0x0184 0048 - 0x0184 0ffc - reserved 0x0184 1000 edmaweight l2 edma access control register 0x0184 1004 - 0x0184 1ffc - reserved 0x0184 2000 l2alloc0 l2 allocation register 0 0x0184 2004 l2alloc1 l2 allocation register 1 0x0184 2008 l2alloc2 l2 allocation register 2 0x0184 200c l2alloc3 l2 allocation register 3 0x0184 2010 - 0x0184 3fff - reserved 0x0184 4000 l2wbar l2 writeback base address register 0x0184 4004 l2wwc l2 writeback word count register 0x0184 4010 l2wibar l2 writeback invalidate base address register 0x0184 4014 l2wiwc l2 writeback invalidate word count register 0x0184 4018 l2ibar l2 invalidate base address register 0x0184 401c l2iwc l2 invalidate word count register 0x0184 4020 l1pibar l1p invalidate base address register 0x0184 4024 l1piwc l1p invalidate word count register 0x0184 4030 l1dwibar l1d writeback invalidate base address register 0x0184 4034 l1dwiwc l1d writeback invalidate word count register 0x0184 4038 - reserved 0x0184 4040 l1dwbar l1d block writeback 0x0184 4044 l1dwwc l1d block writeback 0x0184 4048 l1dibar l1d invalidate base address register 0x0184 404c l1diwc l1d invalidate word count register 0x0184 4050 - 0x0184 4fff - reserved 0x0184 5000 l2wb l2 writeback all register 0x0184 5004 l2wbinv l2 writeback invalidate all register 0x0184 5008 l2inv l2 global invalidate without writeback 0x0184 500c - 0x0184 5027 - reserved 0x0184 5028 l1pinv l1p global invalidate 0x0184 502c - 0x0184 5039 - reserved 0x0184 5040 l1dwb l1d global writeback 0x0184 5044 l1dwbinv l1d global writeback with invalidate 0x0184 5048 l1dinv l1d global invalidate without writeback submit documentation feedback device overview 11
2.4 memory map summary tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-2. c64x+ cache registers (continued) hex address range register acronym description 0x0184 8000 - 0x0184 80bc mar0 - mar47 reserved (corresponds to byte address 0x0000 0000 - 0x2fff ffff) 0x0184 80c0 - 0x0184 80fc mar48 - mar63 reserved (corresponds to byte address 0x3000 0000 - 0x3fff ffff) 0x0184 8100 - 0x0184 8104 mar64 - mar65 reserved (corresponds to byte address 0x4000 0000 - 0x41ff ffff) memory attribute registers for emifa 0x0184 8108 - 0x0184 8124 mar66 - mar73 (corresponds to byte address 0x4200 0000 - 0x49ff ffff) 0x0184 8128 - 0x0184 812c mar74 - mar75 reserved (corresponds to byte address 0x4a00 0000 - 0x4bff ffff) 0x0184 8130 - 0x0184 813c mar76 - mar79 reserved (corresponds to byte address 0x4c00 0000 - 0x4fff ffff) 0x0184 8140- 0x0184 81fc mar80 - mar127 reserved (corresponds to byte address 0x5000 0000 - 0x7fff ffff) memory attribute registers for ddr2 0x0184 8200 - 0x0184 823c mar128 - mar143 (corresponds to byte address 0x8000 0000 - 0x8fff ffff) 0x0184 8240 - 0x0184 83fc mar144 - mar255 reserved (corresponds to byte address 0x9000 0000 - 0xffff ffff) table 2-3 shows the memory map address ranges of the device. table 2-4 depicts the expanded map of the configuration space (0x0180 0000 through 0x0fff ffff). the device has multiple on-chip memories associated with its two processors and various subsystems. to help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. 12 device overview submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-3. memory map summary start end size c64x+ edma peripheral vpss address address (bytes) memory map memory map memory map 0x0000 0000 0x000f ffff 1m reserved 0x0010 0000 0x0010 ffff 64k boot rom 0x0011 0000 0x007f ffff 7m-64k reserved 0x0080 0000 0x0080 ffff 64k reserved 0x0081 0000 0x0081 ffff 64k l2 ram/cache (1) 0x0082 0000 0x00e0 7fff 6048k reserved 0x00e0 8000 0x00e0 ffff 32k l1p ram/cache (1) reserved 0x00e1 0000 0x00f0 3fff 976k reserved 0x00f0 4000 0x00f0 7fff 16k reserved 0x00f0 8000 0x00f0 ffff 32k l1d ram 0x00f1 0000 0x00f1 7fff 32k l1d ram/cache (1) 0x00f1 8000 0x017f ffff 9120k reserved 0x0180 0000 0x01bf ffff 4m cfg space 0x01c0 0000 0x01ff ffff 4m cfg bus peripherals cfg bus peripherals 0x0200 0000 0x100f ffff 225m reserved 0x1010 0000 0x1010 ffff 64k boot rom reserved 0x1011 0000 0x107f ffff 7m-48k reserved 0x1080 0000 0x1080 ffff 64k reserved reserved 0x1081 0000 0x1081 ffff 64k l2 ram/cache (1) l2 ram/cache (1) 0x1082 0000 0x10e0 7fff 6048k reserved reserved 0x10e0 8000 0x10e0 ffff 32k l1p ram/cache (1) l1p ram/cache (1) reserved 0x10e1 0000 0x10f0 3fff 976k reserved reserved 0x10f0 4000 0x10f0 7fff 16k reserved reserved 0x10f0 8000 0x10f0 ffff 32k l1d ram l1d ram 0x10f1 0000 0x10f1 7fff 32k l1d ram/cache (1) l1d ram/cache (1) 0x10f1 8000 0x10ff ffff 1m-96k reserved reserved 0x1100 0000 0x1fff ffff 240m reserved reserved 0x2000 0000 0x2000 7fff 32k ddr2 control regs ddr2 control regs 0x2000 8000 0x2fff ffff 256m-32k reserved reserved 0x3000 0000 0x3fff ffff 256m reserved reserved 0x4000 0000 0x41ff ffff 32m reserved reserved 0x4200 0000 0x42ff ffff 16m emifa data ( cs2) (2) emifa data ( cs2) (2) 0x4300 0000 0x43ff ffff 16m reserved reserved 0x4400 0000 0x44ff ffff 16m emifa data ( cs3) (2) emifa data ( cs3) (2) 0x4500 0000 0x45ff ffff 16m reserved reserved 0x4600 0000 0x46ff ffff 16m emifa data ( cs4) (2) emifa data ( cs4) (2) 0x4700 0000 0x47ff ffff 16m reserved reserved 0x4800 0000 0x48ff ffff 16m emifa data ( cs5) (2) emifa data ( cs5) (2) 0x4900 0000 0x49ff ffff 16m reserved reserved 0x4a00 0000 0x4bff ffff 32m reserved reserved 0x4c00 0000 0x4fff ffff 64m reserved reserved 0x5000 0000 0x7fff ffff 768m reserved reserved 0x8000 0000 0x8fff ffff 256m ddr2 memory controller ddr2 memory controller ddr2 memory controller 0x9000 0000 0xffff ffff 1792m reserved reserved reserved (1) for all bootmodes that default to dspbootaddr = 0x0010 0000 (i.e., all boot modes except the emifa rom direct boot, bootmode[3:0] = 0100, fastboot = 0), the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram (l2cfg.l2mode = 0h, l1pcfg.l1pmode = 0h, and l1dcfg.l1dmode = 0h). if cache use is required, the application code must explicitly enable the cache. for more information on boot modes, see section 3.4.1 , boot modes. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). for the emifa rom direct boot (bootmode[3:0] = 0100, fastboot = 0), the bootloader is not executed?that is, l2 ram/cache defaults to all ram (l2cfg.l2mode = 0h); l1p ram/cache defaults to all cache (l1pcfg.l1pmode = 7h); and l1d ram/cache defaults to all cache (l1dcfg.l1dmode = 7h). (2) the emifa cs0 and cs1 are not functionally supported on the dm6431 device, and therefore, are not pinned out. submit documentation feedback device overview 13
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-4. configuration memory map summary start end size c64x+ address address (bytes) 0x0180 0000 0x0180 ffff 64k c64x+ interrupt controller 0x0181 0000 0x0181 0fff 4k c64x+ powerdown controller 0x0181 1000 0x0181 1fff 4k c64x+ security id 0x0181 2000 0x0181 2fff 4k c64x+ revision id 0x0182 0000 0x0182 ffff 64k c64x+ emc 0x0183 0000 0x0183 ffff 64k reserved 0x0184 0000 0x0184 ffff 64k c64x+ memory system 0x0185 0000 0x0187 ffff 192k reserved 0x0188 0000 0x01bb ffff 3328k reserved 0x01bc 0000 0x01bc 00ff 256 reserved 0x01bc 0100 0x01bc 01ff 256 pin manager and trace 0x01bc 0400 0x01bf ffff 255k reserved 0x01c0 0000 0x01c0 ffff 64k edma cc 0x01c1 0000 0x01c1 03ff 1k edma tc0 0x01c1 0400 0x01c1 07ff 1k edma tc1 0x01c1 0800 0x01c1 0bff 1k edma tc2 0x01c1 0c00 0x01c1 9fff 5k reserved 0x01c1 a000 0x01c1 a7ff 2k reserved 0x01c1 a800 0x01c1 ffff 22k reserved 0x01c2 0000 0x01c2 03ff 1k uart0 0x01c2 0400 0x01c2 07ff 1k reserved 0x01c2 0800 0x01c2 0fff 2k reserved 0x01c2 1000 0x01c2 13ff 1k i2c 0x01c2 1400 0x01c2 17ff 1k timer0 0x01c2 1800 0x01c2 1bff 1k timer1 0x01c2 1c00 0x01c2 1fff 1k timer2 (watchdog) 0x01c2 2000 0x01c2 23ff 1k pwm0 0x01c2 2400 0x01c2 27ff 1k pwm1 0x01c2 2800 0x01c2 2bff 1k pwm2 0x01c2 2c00 0x01c2 2fff 1k reserved 0x01c2 3000 0x01c2 3fff 4k hecc control (1) 0x01c2 4000 0x01c2 53ff 5k hecc ram 0x01c2 5400 0x01c3 ffff 107k reserved 0x01c4 0000 0x01c4 07ff 2k system module 0x01c4 0800 0x01c4 0bff 1k pll controller 1 0x01c4 0c00 0x01c4 0fff 1k pll controller 2 0x01c4 1000 0x01c4 1fff 4k power and sleep controller 0x01c4 2000 0x01c6 6fff 148k reserved 0x01c6 7000 0x01c6 77ff 2k gpio 0x01c6 7800 0x01c6 7fff 2k reserved 0x01c6 8000 0x01c6 ffff 32k reserved 0x01c7 0000 0x01c7 3fff 16k vpss registers 0x01c7 4000 0x01c7 ffff 48k reserved 0x01c8 0000 0x01c8 0fff 4k emac control registers 0x01c8 1000 0x01c8 1fff 4k emac control module registers (1) software must not access "reserved" locations of the hecc. access to hecc "reserved" locations may hang the device. device overview 14 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-4. configuration memory map summary (continued) start end size c64x+ address address (bytes) 0x01c8 2000 0x01c8 3fff 8k emac control module ram 0x01c8 4000 0x01c8 47ff 2k mdio control registers 0x01c8 4800 0x01cf ffff 494k reserved 0x01d0 0000 0x01d0 07ff 2k mcbsp0 0x01d0 0800 0x01d0 0fff 2k reserved 0x01d0 1000 0x01d0 13ff 1k mcasp0 control 0x01d0 1400 0x01d0 17ff 1k mcasp0 data 0x01d0 1800 0x01df ffff 1018k reserved 0x01e0 0000 0x01e0 0fff 4k emifa control 0x01e0 1000 0x01e0 1fff 4k reserved 0x01e0 2000 0x0fff ffff 226m-8k reserved submit documentation feedback device overview 15
2.5 pin assignments 2.5.1 pin map (bottom view) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. for more information on pin muxing, see section 3.7 , multiplexed pin configurations of this document. figure 2-2 through figure 2-5 show the bottom view of the zwt package pin assignments in four quadrants (a, b, c, and d). figure 2-6 through figure 2-9 show the bottom view of the zdu package pin assignments in four quadrants (a, b, c, and d). figure 2-2. zwt pin map [quadrant a] device overview 16 submit documentation feedback w v u t r p nm l k 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 ddr_d[3] v ss hecc_tx/ tout1l/ gp[55] v ss ucts0/ gp[87] utxd0/ gp[86] urxd0/ gp[85] scl sda tck resetout emu1 por dv dd33 tdo emu0 trst dv ddr2 tms ddr_d[1] ddr_dqm[0] ddr_d[2] rsv16 tdi reset rsv3 hecc_rx/ tinp1l/ gp[56] rsv2 cv dd v ss v ss v ss cv dd dv ddr2 ddr_a[11] ddr_a[12] ddr_clk ddr_clk ddr_d[14] v ss dv dd33 v ss ddr_d[5] ddr_d[6] ddr_d[9] v ss v ss dv ddr2 ddr_ba[2] v ss ddr_d[11] ddr_d[15] ddr_cke cv dd v ss cv dd cv dd v ss ddr_dqm[1] ddr_cas ddr_we ddr_zn v ss v ss ddr_dqs[1] ddr_ras ddr_a[10] cv dd cv dd dv ddr2 ddr_d[4] ddr_d[8] ddr_d[13] ddr_ba[1] ddr_d[12] dv ddr2 tinp0l/ gp[98] v ss v ss v ss dv ddr2 clkout0/ pwm2/ gp[84] dv dd33 v ss dv dd33 dv ddr2 dv ddr2 v ss dv ddr2 ddr_cs cv dd ddr_dqs[0] ddr_d[10] ddr_ba[0] ddr_d[0] urts0/ pwm0/ gp[88] ddr_d[7] w v u t r p nm l k v ss v ss ddr_a[8] ddr_a[8]
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 2-3. zwt pin map [quadrant b] submit documentation feedback device overview 17 w v u t r p nm l k 19 18 17 16 15 14 13 12 11 19 18 17 16 15 14 13 12 11 rsv14 cv dd v ss v ss cv dd v ss cv dd v ss v ss v ss dv ddr2 v ss rsv5 dv ddr2 ddr_zp ddr_vssdll ddr_vdddll dv ddr2 cv dd dv ddr2 v ss v ss v ss v ss v ss rsv9 rsv6 rsv8 dv ddr2 dv ddr2 rsv35 rsv29 rsv26 rsv7 rsv4 dv ddr2 v ss dv ddr2 rsv22 rsv36 mxv dd rsv25 rsv30 rsv32 v ss v ss rsv12rsv10 v ss rsv15 ddr_vref rsv21 rsv31 rsv39 dv dd33 mxi/ clkin rsv28 rsv23 rsv38 v ss v ss rsv27 rsv37 rsv24 v ss cv dd dv dd33 v ss pll pwr18 v ss v ss dv dd33 rsv13 v ss rsv11 v ss rsv34 mxv ss rsv20 rsv33 cv dd w v u t r p nm l k ddr_a[0]ddr_a[1] ddr_a[2] ddr_a[5]ddr_a[3] ddr_a[4] ddr_a[6]ddr_a[9] ddr_a[7]
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 2-4. zwt pin map [quadrant c] 18 device overview submit documentation feedback h g f e dc b a 19 18 17 16 15 14 13 12 11 19 18 17 16 15 14 13 12 11 cv dd em_wait/ (rdy/bsy ) vd/ gp[53] yi7(ccd7)/ gp[43] em_a[15]/ gp[49] em_a[16]/ gp[48] ci0(ccd8)/ em_a[20]/ gp[44] c_field/ em_a[21]/ gp[34] em_a[18]/ gp[46] c_we/ em_r/w / gp[35] rsv19 rsv18 dv dd33 dv dd33 v ss v ss v ss dv dd33 v ss yi5(ccd5)/ gp[41] yi3(ccd3)/ gp[39] yi6(ccd6)/ gp[42] pclk/ gp[54] em_cs3 / gp[13] em_cs2 / gp[12] gp[22]/ (bootmode0) em_d[1]/ gp[15] gp[31] em_d[4]/ gp[18] em_cs4 / gp[32] yi1(ccd1)/ gp[37] em_d[6]/ gp[20] v ss yi4(ccd4)/ gp[40] v ss dv dd33 dv dd33 em_a[3]/ gp[11] em_a[1]/ (ale)/gp[9]/ (aeaw1/ pllms1) em_d[5]/ gp[19] em_d[2]/ gp[16] em_ba[1]/ gp[5]/ (aem0) em_d[0]/ gp[14] gp[24]/ (bootmode2) gp[25]/ (bootmode3) gp[26]/ (fastboot) gp[30] em_a[4]/ gp[10]/ (aeaw2/ pllms2) v ss gp[29] gp[28] v ss em_a[0]/ gp[7]/ (aem2) v ss em_a[17]/ gp[47] hd/ gp[52] em_ba[0]/ gp[6]/ (aem1) em_a[2]/ (cle)/gp[8]/ (aeaw0/ pllms0) em_d[7]/ gp[21] yi2(ccd2)/ gp[38] yi0(ccd0)/ gp[36] em_oe em_we em_d[3]/ gp[17] gp[23]/ (bootmode1) v ss dv dd33 cv dd v ss gp[27] ci1(ccd9)/ em_a[19]/ gp[45] h g f e dc b a j v ss cv dd v ss v ss dv dd33 mxo v ss dv dd33 v ss j em_cs5 / gp[33]
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 2-5. zwt pin map [quadrant d] submit documentation feedback device overview 19 j hg fe dc ba 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 axr0[0]/ gp[105] dv dd33 mtxclk/ gp[73] dv dd33 v ss mrxclk/ gp[77] mrxd1/ gp[79] mrxd3/ gp[82] mrxd0/ gp[78] mdio/ gp[83] mtxen/ gp[75] mrxd2/ gp[80] mtxd0/ gp[72] gp[0] gp[2] gp[1] amutein0/ gp[109] v ss gp[4]/ pwm1 afsx0/ gp[107] axr0[3]/ fsr0/ gp[102] aclkr0/ clkx0/ gp[99] amute0/ gp[110] gp[3] mrxdv/ gp[74] mcrs/ gp[68] mtxd1/ gp[71] gp[66] em_a[7]/ gp[94] em_a[11]/ gp[90] em_a[9]/ gp[92] em_a[12]/ gp[89] v ss rsv17 gp[65] dv dd33 axr0[2]/ fsx0/ gp[103] axr0[1]/ dx0/ gp[104] mtxd2/ gp[70] dv dd33 v ss cv dd em_a[8]/ gp[93] v ss v ss cv dd cv dd gp[57] dv dd33 em_a[6]/ gp[95] gp[62] gp[59] dv dd33 v ss dv dd33 dv dd33 gp[60] em_a[14]/ gp[50] v ss cv dd v ss em_a[5]/ gp[96] em_a[13]/ gp[51] dv dd33 ahclkr0/ clkr0/ gp[101] clks0/ tout0l/ gp[97] dv dd33 v ss v ss dv dd33 gp[63] gp[58] gp[61] v ss mdclk/ gp[81] mtxd3/ gp[69] mcol/gp[67] gp[64] rsv1 v ss aclkx0/ gp[106] v ss v ss afsr0/ dr0/ gp[100] dv dd33 v ss ahclkx0/ gp[108] mrxer/ gp[76] j h g f e dc ba dv dd33 em_a[10]/ gp[91]
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 2-6. zdu pin map [quadrant a] 20 device overview submit documentation feedback m n p r t u v 11 10 9 4 3 11 10 9 8 7 6 5 4 3 m n v w w y y 2 1 2 1 aa aa ab ab m n p r t u p 11 5 10 9 8 7 6 clkout0/ pwm2/ gp[84] reset resetout por tms tdo tdi tck trst emu1 emu0 rsv16 dv dd33 dv dd33 dv dd33 dv dd33 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 urts0/ pwm0/ gp[88] hecc_rx/ tinp1l/ gp[56] hecc_tx/ tout1l/ gp[55] v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss cv dd v ss v ss v ss v ss v ss rsv3 ucts0/ gp[87] utxd0/ gp[86] urxd0/ gp[85] sda scl ddr_d[0] ddr_d[1] ddr_d[2] ddr_d[3] ddr_d[4] ddr_d[5] ddr_d[6] ddr_d[7] ddr_d[8] ddr_d[9] ddr_d[10] ddr_d[11] ddr_d[12] ddr_d[13]ddr_d[14] ddr_d[15] ddr_a[11] ddr_a[10] ddr_a[12] ddr_bs[2] ddr_bs[1]ddr_bs[0] ddr_dqs[1] ddr_dqs[0] ddr_cas ddr_ras ddr_dqm[0] ddr_dqm[1] ddr_cs ddr_we ddr_cke ddr_clk0 ddr_clk0 cv dd cv dd v ss cv dd v ss v ss cv dd
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 2-7. zdu pin map [quadrant b] submit documentation feedback device overview 21 m n p r t u v 12 13 14 19 20 12 13 14 15 16 17 18 19 20 m n v w w y y 21 22 21 22 aa aa ab ab m n p r t u p 12 18 13 14 15 16 17 mxi/ clkin mxo mxv ss pll pwr18 rsv6 rsv7 rsv8 rsv9 rsv10 rsv12 rsv11 rsv13 rsv14 rsv15 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 mxv dd dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 cv dd cv dd cv dd cv dd v ss v ss v ss rsv32 rsv28 rsv20 ddr_a[5] v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss rsv4 v ss v ss v ss v ss rsv5 ddr_zp ddr_zn ddr_vdddll ddr_vssdll ddr_vref rsv24rsv25 rsv26 rsv27 rsv29 rsv30 rsv31 rsv33 rsv34 rsv35 rsv36 rsv37 rsv38 rsv39 ddr_a[0] ddr_a[1] ddr_a[2] ddr_a[3] ddr_a[4]ddr_a[6] ddr_a[7] ddr_a[8] ddr_a[9] rsv23 rsv22 rsv21 v ss
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 2-8. zdu pin map [quadrant c] 22 device overview submit documentation feedback l k j h g fe 12 13 14 19 20 12 13 14 15 16 17 18 19 20 l k e d v ss em_ba[0]/ gp[6]/ (aem1) dv dd33 dv dd33 rsv19 rsv18 em_oe v ss rsv17 d c c_we/ em_r/w / gp[35] em_ba[1]/ gp[5[/ (aem0) c_field/ em_a[21]/ gp[34] ci1(ccd9)/ em_a[19]/ gp[45] em_a[15]/ gp[49] em_we ci0(ccd8)/ em_a[20]/ gp[44] em_a[11]/ gp[90] c 21 22 21 22 em_d[2]/ gp[16] em_d[5]/ gp[19] em_d[6]/ gp[20] em_d[4]/ gp[18] em_cs4 / gp[32] em_cs5 / gp[33] gp[29] dv dd33 em_d[0]/ gp[14] gp[31] gp[30] v ss em_cs3 / gp[13] em_a[3]/ gp[11] em_cs2 / gp[12] b yi2(ccd2) gp[38] yi4(ccd4)/ gp[40] yi1(ccd1)/ gp[37] em_a[17]/ gp[47] em_a[16]/ gp[48] yi0(ccd0)/ gp[36] yi6(ccd6)/ gp[42] em_a[12]/ gp[89] b a yi7(ccd7)/ gp[43] pclk/ gp[54] yi3(ccd3)/ gp[39] em_a[18]/ gp[46] em_a[14]/ gp[50] hd/ gp[52] vd/ gp[53] em_a[13]/ gp[51] a v ss v ss dv dd33 13 14 15 16 17 lk j hg f j 12 18 gp[27] gp[25]/ (bootmode3) gp[24]/ (bootmode2) gp[23]/ (bootmode1) gp[28] gp[26]/ (fastboot) em_a[4]/ gp[10]/ (aeaw2/ pllms2) em_a[1]/ (ale)/gp[9]/ (aeaw1/ pllms1)em_a[2]/ (cle)/gp[8]/ (aeaw0/ pllms0) em_a[0]/ gp[7]/ (aem2) em_wait/ (rdy/bsy ) gp[22]/ (bootmode0) dv dd33 dv dd33 dv dd33 v ss v ss v ss v ss dv dd33 v ss v ss dv dd33 dv dd33 v ss dv dd33 dv dd33 dv dd33 cv dd cv dd cv dd v ss cv dd cv dd v ss v ss v ss v ss v ss em_d[7]/ gp[21] em_d[3]/ gp[17] em_d[1]/ gp[15] yi5(ccd5)/ gp[41]
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 2-9. zdu pin map [quadrant d] submit documentation feedback device overview 23 l k j hg f e 11 10 9 4 3 11 10 9 8 7 6 5 4 3 l k e d dv dd33 mrxdv/ gp[74] v ss dv dd33 rsv1 dv dd33 v ss d c mcol/gp[67] mrxd2/ gp[80] mtxd2/ gp[70] gp[64] gp[59] em_a[7]/ gp[94] mtxen/ gp[75] gp[62] em_a[9]/ gp[92] c 2 1 2 1 gp[0] gp[2] gp[3] afsx0/ gp[107] ahclkx0/ gp[108] axr0[0]/ gp[105] aclkr0/ clkx0/ gp[99] axr0[2]/ fsx0/ gp[103] axr0[1]/ dx0/ gp[104] tinp0l/ gp[98] gp[1] aclkx0/ gp[106] ahclkr0/ clkr0/ gp[101] dv dd33 mdio/ gp[83] mrxd3/ gp[82] mdclk/ gp[81] mrxd0/ gp[78] b mcrs/ gp[68] mrxd1/ gp[79] mtxd0/ gp[72] gp[65] gp[58] em_a[6]/ gp[95] mtxd1/ gp[71] gp[61] em_a[10]/ gp[91] b a gp[66] mrxclk/ gp[77] mtxd3/ gp[69] gp[63] gp[60] em_a[5]/ gp[96] mtxclk/ gp[73] gp[57] em_a[8]/ gp[93] a dv dd33 mrxer/ gp[76] v ss dv dd33 11 10 9 8 7 6 l k jh g f j 5 dv dd33 dv dd33 dv dd33 dv dd33 v ss dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 gp[4]/ pwm1 tout0l/ gp[97] v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss rsv2 amute0/ gp[110] amutein0/ gp[109] afsr0/ dr0/ gp[100] axr0[3]/ fsr0/ gp[102] cv dd cv dd cv dd cv dd
2.6 terminal functions tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the terminal functions tables (table 2-5 through table 2-26 ) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. for more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations, see the device configurations section of this data manual. all device boot and configuration pins are multiplexed configuration pins? meaning they are multiplexed with functional pins. these pins function as device boot and configuration pins only during device reset. the input states of these pins are sampled and latched into the bootcfg register when device reset is deasserted (see note below). after device reset is deasserted, the values on these multiplexed pins no longer have to hold the configuration. for proper device operation, external pullup/pulldown resistors may be required on these device boot and configuration pins. section 3.9.1 , pullup/pulldown resistors discusses situations where external pullup/pulldown resistors are required. note: internal to the chip, the two device reset pins reset and por are logically and?d together for the purpose of latching device boot and configuration pins. the values on all device boot and configuration pins are latched into the bootcfg register when the logical and of reset and por transitions from low-to-high. 24 device overview submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-5. boot terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. boot gp[25]/ (bootmode3) g16 h21 bootmode configuration bits. these bootmode functions along with gp[24]/ the fastboot function determine what device bootmode (bootmode2) g15 l20 ipd configuration is selected. i/o/z dv dd33 the dm6431 device supports several types of bootmodes along with gp[23]/ f15 k20 a fastboot option; for more details on the types/options, see (bootmode1) f18 j20 section 3.4.1 , boot modes. gp[22]/ (bootmode0) fast boot gp[26]/ ipd g17 k19 i/o/z 0 = not fast boot (fastboot) dv dd33 1 = fast boot em_a[4]/gp[10]/ ipd emifa address bus width (aeaw) and fast boot pll multiplier a17 b21 i/o/z (aeaw2/pllms2) dv dd33 select (pllms). these configuration pins serve two purposes which are based on em_a[1]/(ale)/ ipd aem[2:0] settings. gp[9]/ a16 b20 i/o/z dv dd33 for aem[2:0] = 001 [8-bit emifa (async) pinout mode 1], the (aeaw1/pllms1) aeaw/pllms pins serve as the aeaw function to select emifa address bus width. em_a[2]/(cle)/ for all other aem modes, the aeaw/pllms pins select the pll ipd gp[8]/ b16 a20 i/o/z multiplier for fast boot. dv dd33 (aeaw0/pllms0) for more details, see section 3.5.1.2 , emifa address width select (aeaw) and fast boot pll multipler select (pllms). em_a[0]/ ipd selects emifa pinout mode b17 c21 i/o/z gp[7]/(aem2) dv dd33 the dm6431 supports the following emifa pinout modes: em_ba[0]/ ipd c17 e20 i/o/z aem[2:0] = 000, no emifa gp[6]/(aem1) dv dd33 aem[2:0] = 001, 8-bit emifa (async) pinout mode 1 aem[2:0] = 101, 8-bit emifa (nand) pinout mode 5 em_ba[1]/ ipd c16 c20 i/o/z gp[5]/(aem0) dv dd33 this signal doesn't actually affect the emifa module. it only affects how the emifa is pinned out. for proper dm6431 device operation, if this pin is both routed and 3-stated (not driven) during device reset, it must be pulled down via ipd gp[28] h16 j21 i/o/z an external resistor. for more detailed information on dv dd33 pullup/pulldown resistors, see section 3.9.1 , pullup/pulldown resistors. for proper dm6431 device operation, if this pin is both routed and ipu 3-stated (not driven) during device reset, it must be pulled up via an gp[27] h17 l19 i/o/z dv dd33 external resistor. for more detailed information on pullup/pulldown resistors, see section 3.9.1 , pullup/pulldown resistors. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 25
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-6. oscillator/pll terminal functions signal type (1) other (2) description zwt zdu name no. no. oscillator, pll crystal input mxi for mx oscillator (system oscillator, typically 27 mhz). mxi/ k19 n22 i mxv dd if the internal oscillator is bypassed, this is the external oscillator clock clkin input. (3) mxo j19 m22 o mxv dd crystal output for mx oscillator 1.8 v power supply for mx oscillator. on the board, this pin can be mxv dd l18 n21 s (4) connected to the same 1.8 v power supply as dv ddr2 . mxv ss k18 m21 gnd (4) ground for mx oscillator pll pwr18 l16 n20 s (4) 1.8 v power supply for plls (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) specifies the operating i/o supply voltage for each signal (3) for more information on external board connections, see section 6.6 , external clock input from mxi/clkin pin. (4) for more information, see the recommended operating conditions table table 2-7. clock generator terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. clock generator this pin is multiplexed between the system clock generator (pll1), pwm2, and gpio. clkout0/ ipd m1 r1 i/o/z for the system clock generator (pll1), it is clock output clkout0. this is pwm2/gp[84] dv dd33 configurable for 27 mhz or other 27 mhz-divided-down (/1 to /32) clock outputs. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 26 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-8. reset and jtag terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. reset ipu reset m4 r3 i device reset dv dd33 ? reset output status pin. the resetout pin indicates when the resetout n3 t3 o/z dv dd33 device is in reset. ipu por n4 r2 i power-on reset. dv dd33 jtag ipu jtag test-port mode select input. tms r3 v3 i dv dd33 for proper device operation, do not oppose the ipu on this pin. ? tdo p3 u2 o/z jtag test-port data output dv dd33 ipu tdi p4 u3 i jtag test-port data input dv dd33 ipu tck n1 u1 i jtag test-port clock input dv dd33 jtag test-port reset. for ieee 1149.1 jtag compatibility, see ipd trst r2 v2 i the ieee 1149.1 jtag compatibility statement portion of this data dv dd33 sheet ipu emu1 n2 t2 i/o/z emulation pin 1 dv dd33 ipu emu0 p2 t1 i/o/z emulation pin 0 dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 27
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-9. emifa terminal functions (boot configuration) signal type (1) other (2) (3) description zwt zdu name no. no. emifa: boot configuration em_a[4]/gp[10]/ ipd these pins are multiplexed between the emifa and gpio. when a17 b21 i/o/z (aeaw2/pllms2) dv dd33 reset or por is asserted, these pins function as emifa configuration pins. at reset if aem[2:0] = 001 (emifa in 8-bit async em_a[1]/(ale)/gp[ ipd mode), then the input states of aeaw[2:0] are sampled to set the 9]/ a16 b20 i/o/z dv dd33 emifa address bus width. after reset, these pins function as emifa (aeaw1/pllms1) or gpio pin functions based on pin mux selection. em_a[2]/(cle)/gp for more details on the aeaw/pllms functions, see section 3.5.1.2 , ipd [8]/ b16 a20 i/o/z emifa address bus width (aeaw) and fast boot pll multiplier dv dd33 (aeaw0/pllms0) select (pllms). em_ba[1]/ ipd these pins are multiplexed between the emifa and gpio. when c16 c20 i/o/z gp[5]/(aem0) dv dd33 reset or por is asserted, these pins function as emifa configuration pins. at reset, the input states of aem[2:0] are sampled em_ba[0]/ ipd c17 e20 i/o/z to set the emifa pinout mode. gp[6]/(aem1) dv dd33 for more details, see section 3.5.1 , configurations at reset. after reset, these pins function as emifa or gpio pin functions based on em_a[0]/ ipd pin mux selection. b17 c21 i/o/z gp[7]/(aem2) dv dd33 for more details on the aem functions, see section 3.5.1.1 , emifa pinout mode (aem[2:0]). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 28 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-10. emifa terminal functions (emifa pinout mode 1, aem[2:0] = 001) signal type (1) other (2) (3) description zwt zdu name no. no. emifa functional pins: 8-bit async/nor (emifa pinout mode 1, aem[2:0] = 001) actual pin functions are determined by the pinmux0 and pinmux1 register bit settings (e.g., aeaw[2:0], aem[2:0], etc.). for more details, see section 3.7 , multiplexed pin configurations this pin is multiplexed between emifa and gpio. for emifa, this pin is chip select 2 output em_cs2 for use with asynchronous memories (i.e., nor flash). ipd this is the chip select for the default boot and rom boot modes. em_cs2/gp[12] c19 c22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa and gpio. for emifa, this pin is chip select 3 output em_cs3 for use with asynchronous memories (i.e., nor flash). ipd em_cs3/gp[13] c18 d22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa and gpio. for emifa, it is chip select 4 output em_cs4 for use with asynchronous memories (i.e., nor flash). ipd em_cs4/gp[32] e19 h22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa and gpio. for emifa, it is chip select 5 output em_cs5 for use with asynchronous memories (i.e., nor flash). ipd em_cs5/gp[33] f19 j22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpfe (ccdc), emifa, and gpio. c_we/em_r/ w/ ipd d13 c17 i/o/z gp[35] dv dd33 for emifa, it is read/write output em_r/ w. em_wait/ ipu for emifa (async/nor), this pin is wait state extension input e15 d20 i/o/z (rdy/ bsy) dv dd33 em_wait. ipu em_oe d15 d19 i/o/z for emifa, it is output enable output em_oe. dv dd33 ipu em_we e14 c19 i/o/z for emifa, it is write enable output em_we. dv dd33 this pin is multiplexed between emifa and gpio. em_ba[0]/ ipd for emifa, this is the bank address 0 output (em_ba[0]). when c17 e20 i/o/z gp[6]/(aem1) dv dd33 connected to an 8-bit asynchronous memory, this pin is the lowest order bit of the byte address. this pin is multiplexed between emifa and gpio. em_ba[1]/ ipd for emifa, this is the bank address 1 output em_ba[1]. when c16 c20 i/o/z gp[5]/(aem0) dv dd33 connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 29
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-10. emifa terminal functions (emifa pinout mode 1, aem[2:0] = 001) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. this pin is multiplexed between vpfe (ccdc), emifa, and gpio. c_field/ ipd d12 c16 i/o/z em_a[21]/gp[34] dv dd33 for emifa, it is address bit 21 output em_a[21]. this pin is multiplexed between vpfe (ccdc), emifa, and gpio. ci0(ccd8)/ ipd c12 c15 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 20 output em_a[20]/gp[44] dv dd33 em_a[20] if aeaw[2:0] = 100b. this pin is multiplexed between vpfe (ccdc), emifa, and gpio. ci1(ccd9)/ ipd b12 c14 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 19 output em_a[19]/gp[45] dv dd33 em_a[19] if aeaw[2:0] = 100b. this pin is multiplexed between emifa and gpio. ipd em_a[18]/gp[46] d11 a14 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 18 output dv dd33 em_a[18] if aeaw[2:0] = 011/100b. this pin is multiplexed between emifa and gpio. ipd em_a[17]/gp[47] a11 b14 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 17 output dv dd33 em_a[17] if aeaw[2:0] = 011/100b. this pin is multiplexed between emifa and gpio. ipd em_a[16]/gp[48] c11 b13 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 16 output dv dd33 em_a[16] if aeaw[2:0] = 010/011/100b. this pin is multiplexed between emifa and gpio. ipd em_a[15]/gp[49] b11 c13 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 15 output dv dd33 em_a[15] if aeaw[2:0] = 010/011/100b. this pin is multiplexed between emifaand gpio. ipd em_a[14]/gp[50] a10 a13 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 14 output dv dd33 em_a[14] if aeaw[2:0] = 001/010/011/100b. this pin is multiplexed between emifa and gpio. ipd em_a[13]/gp[51] b10 a12 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 13 output dv dd33 em_a[13] if aeaw[2:0] = 001/010/011/100b. this pin is multiplexed between emifa and gpio. ipd em_a[12]/gp[89] d10 b12 i/o/z dv dd33 for emifa, this pin is address bit 12 output em_a[12]. this pin is multiplexed between emifa and gpio. ipd em_a[11]/gp[90] c10 c12 i/o/z dv dd33 for emifa, this pin is address bit 11 output em_a[11]. this pin is multiplexed between emifa and gpio. ipd em_a[10]/gp[91] a9 b11 i/o/z dv dd33 for emifa, this pin is address bit 10 output em_a[10]. this pin is multiplexed between emifa and gpio. ipd em_a[9]/gp[92] d9 c11 i/o/z dv dd33 for emifa, this pin is address bit 9 output em_a[9]. this pin is multiplexed between emifa and gpio. ipd em_a[8]/gp[93] b9 a11 i/o/z dv dd33 for emifa, this pin is address bit 8 output em_a[8]. this pin is multiplexed between emifa and gpio. ipd em_a[7]/gp[94] c9 c10 i/o/z dv dd33 for emifa, this pin is address bit 7 output em_a[7]. this pin is multiplexed between emifa and gpio. ipd em_a[6]/gp[95] d8 b10 i/o/z dv dd33 for emifa, this pin is address bit 6 output em_a[6]. this pin is multiplexed between emifa and gpio. ipd em_a[5]/gp[96] b8 a10 i/o/z dv dd33 for emifa, this pin is address bit 5 output em_a[5]. this pin is multiplexed between emifa and gpio. em_a[4]/gp[10]/ ipd a17 b21 i/o/z (aeaw2/pllms2) dv dd33 for emifa, this pin is address bit 4 output em_a[4]. device overview 30 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-10. emifa terminal functions (emifa pinout mode 1, aem[2:0] = 001) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. this pin is multiplexed between emifa and gpio. ipd em_a[3]/gp[11] b18 d21 i/o/z dv dd33 for emifa, this pin is address bit 3 output em_a[3]. em_a[2]/(cle)/gp this pin is multiplexed between emifa and gpio. ipd [8]/ b16 a20 i/o/z dv dd33 for emifa, this pin is address bit 2 output em_a[2]. (aeaw0/pllms0) em_a[1]/(ale)/gp[ this pin is multiplexed between emifa and gpio. ipd 9]/ a16 b20 i/o/z dv dd33 for emifa, this pin is address output em_a[1]. (aeaw1/pllms1) this pin is multiplexed between emifa and gpio. for emifa, this pin is address output em_a[0], which is the least em_a[0]/ ipd b17 c21 i/o/z significant bit on a 32-bit word address. gp[7]/(aem2) dv dd33 for an 8-bit asynchronous memory, this pin is the 3rd bit of the address. ipd em_d0/gp[14] d16 e21 i/o/z dv dd33 ipd em_d1/gp[15] d18 g20 i/o/z dv dd33 ipd em_d2/gp[16] d17 e22 i/o/z dv dd33 ipd these pins are multiplexed between emifa and gpio. em_d3/gp[17] e16 f20 i/o/z dv dd33 for emifa (aem[2:0] = 001), these pins are the 8-bit bi-directional ipd em_d4/gp[18] e18 g21 i/o/z data bus (em_d[7:0]). dv dd33 ipd em_d5/gp[19] e17 f22 i/o/z dv dd33 ipd em_d6/gp[20] f16 f21 i/o/z dv dd33 ipd em_d7/gp[21] f17 h20 i/o/z dv dd33 emifa functional pins: 8-bit nand (emifa pinout mode 1, aem[2:0] = 001) this pin is multiplexed between emifa (nand) and gpio. em_a[1]/(ale)/gp[ ipd 9]/ a16 b20 i/o/z when used for emifa (nand) , this pin is the address latch enable dv dd33 (aeaw1/pllms1) output (ale). this pin is multiplexed between emifa (nand) and gpio. em_a[2]/(cle)/gp ipd [8]/ b16 a20 i/o/z when used for emifa (nand), this pin is the command latch enable dv dd33 (aeaw0/pllms0) output (cle). em_wait/ ipu e15 d20 i/o/z when used for emifa (nand), it is ready/busy input (rdy/ bsy). (rdy/ bsy) dv dd33 ipu em_oe d15 d19 i/o/z when used for emifa (nand), this pin is read enable output ( re). dv dd33 ipu em_we e14 c19 i/o/z when used for emifa (nand), this pin is write enable output ( we). dv dd33 this pin is multiplexed between emifa (nand) and gpio. for emifa (nand), this pin is chip select 2 output em_cs2 for use with nand flash. ipd this is the chip select for the default boot and rom boot modes. em_cs2/gp[12] c19 c22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. submit documentation feedback device overview 31
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-10. emifa terminal functions (emifa pinout mode 1, aem[2:0] = 001) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. this pin is multiplexed between emifa (nand) and gpio. for emifa (nand), this pin is chip select 3 output em_cs3 for use with nand flash. ipd em_cs3/gp[13] c18 d22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa (nand) and gpio. for emifa (nand), it is chip select 4 output em_cs4 for use with nand flash. ipd em_cs4/gp[32] e19 h22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa (nand) and gpio. for emifa (nand), it is chip select 5 output em_cs5 for use with nand flash. ipd em_cs5/gp[33] f19 j22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. ipd em_d0/gp[14] d16 e21 i/o/z dv dd33 ipd em_d1/gp[15] d18 g20 i/o/z dv dd33 ipd em_d2/gp[16] d17 e22 i/o/z dv dd33 ipd these pins are multiplexed between emifa (nand) and gpio. em_d3/gp[17] e16 f20 i/o/z dv dd33 for emifa (nand) aem[2:0] = 001, these are the 8-bit bi-directional ipd em_d4/gp[18] e18 g21 i/o/z data bus (em_d[7:0]). dv dd33 ipd em_d5/gp[19] e17 f22 i/o/z dv dd33 ipd em_d6/gp[20] f16 f21 i/o/z dv dd33 ipd em_d7/gp[21] f17 h20 i/o/z dv dd33 32 device overview submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-11. emifa terminal functions (emifa pinout mode 5, aem[2:0] = 101) signal type (1) other (2) (3) description zwt zdu name no. no. emifa functional pins: 8-bit nand (emifa pinout mode 5, aem[2:0] = 101) actual pin functions are determined by the pinmux0 and pinmux1 register bit settings (e.g., aeaw[2:0], aem[2:0], etc.). for more details, see section 3.7 , multiplexed pin configurations this pin is multiplexed between emifa (nand) and gpio. em_a[1]/(ale)/gp[ ipd 9]/ a16 b20 i/o/z when used for emifa (nand) , this pin is the address latch enable dv dd33 (aeaw1/pllms1) output (ale). this pin is multiplexed between emifa (nand) and gpio. em_a[2]/(cle)/gp ipd [8]/ b16 a20 i/o/z when used for emifa (nand) , this pin is the command latch dv dd33 (aeaw0/pllms0) enable output (cle). em_wait/ ipu e15 d20 i/o/z when used for emifa (nand), it is ready/busy input (rdy/ bsy). (rdy/ bsy) dv dd33 ipu em_oe d15 d19 i/o/z when used for emifa (nand), this pin is read enable output ( re). dv dd33 ipu em_we e14 c19 i/o/z when used for emifa (nand), this pin is write enable output ( we). dv dd33 this pin is multiplexed between emifa (nand) and gpio. for emifa, this pin is chip select 2 output em_cs2 for use with nand flash. ipd this is the chip select for the default boot and rom boot modes. em_cs2/gp[12] c19 c22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa (nand) and gpio. for emifa, this pin is chip select 3 output em_cs3 for use with nand flash. ipd em_cs3/gp[13] c18 d22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa (nand) and gpio. for emifa, it is chip select 4 output em_cs4 for use with nand flash. ipd em_cs4/gp[32] e19 h22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa (nand) and gpio. for emifa, it is chip select 5 output em_cs5 for use with nand flash. ipd em_cs5/gp[33] f19 j22 i/o/z dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 33
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-11. emifa terminal functions (emifa pinout mode 5, aem[2:0] = 101) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. ipd em_d0/gp[14] d16 e21 i/o/z dv dd33 ipd em_d1/gp[15] d18 g20 i/o/z dv dd33 ipd em_d2/gp[16] d17 e22 i/o/z dv dd33 ipd these pins are multiplexed between emifa (nand) and gpio. em_d3/gp[17] e16 f20 i/o/z dv dd33 for emifa aem[2:0] = 101 (nand), these are the 8-bit bi-directional ipd em_d4/gp[18] e18 g21 i/o/z data bus (em_d[7:0]). dv dd33 ipd em_d5/gp[19] e17 f22 i/o/z dv dd33 ipd em_d6/gp[20] f16 f21 i/o/z dv dd33 ipd em_d7/gp[21] f17 h20 i/o/z dv dd33 device overview 34 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-12. ddr2 memory controller terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. ddr2 memory controller ddr_clk w7 ab7 i/o/z dv ddr2 ddr2 clock output ddr_clk w8 ab8 i/o/z dv ddr2 ddr2 differential clock output ddr_cke v8 aa8 i/o/z dv ddr2 ddr2 clock enable output ddr_cs t9 y11 i/o/z dv ddr2 ddr2 active low chip select output ddr_we t8 y10 i/o/z dv ddr2 ddr2 active low write enable output ddr_dqm[1] t6 y7 i/o/z dv ddr2 ddr2 data mask outputs dqm1: for ddr_d[15:8] ddr_dqm[0] t4 y4 i/o/z dv ddr2 dqm0: for lower byte ddr_d[7:0] ddr_ras u7 y8 i/o/z dv ddr2 ddr2 row access signal output ddr_cas t7 y9 i/o/z dv ddr2 ddr2 column access signal output ddr_dqs[0] u4 aa4 i/o/z dv ddr2 data strobe input/outputs for each byte of the 16-bit data bus. they are outputs to the ddr2 memory when writing and inputs when reading. they are used to synchronize the data transfers. ddr_dqs[1] u6 aa7 i/o/z dv ddr2 dqs1: for ddr_d[15:8] dqs0: for bottom byte ddr_d[7:0] ddr_ba[0] u8 aa9 bank select outputs (bs[2:0]). two are required to support 1gb ddr2 ddr_ba[1] v9 ab9 i/o/z dv ddr2 memories. ddr_ba[2] u9 ab10 ddr_a[12] w9 aa10 ddr_a[11] w10 aa11 ddr_a[10] u10 ab11 ddr_a[9] u11 aa12 ddr_a[8] v10 y12 ddr_a[7] v11 ab12 ddr_a[6] w11 aa13 i/o/z dv ddr2 ddr2 address bus output ddr_a[5] w12 y13 ddr_a[4] v12 ab13 ddr_a[3] u12 aa14 ddr_a[2] v13 y14 ddr_a[1] u13 ab14 ddr_a[0] w13 ab15 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) fore more information, see the recommended operating conditions table submit documentation feedback device overview 35
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-12. ddr2 memory controller terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. ddr_d[15] v7 ab6 ddr_d[14] w6 y6 ddr_d[13] v6 aa6 ddr_d[12] w5 ab5 ddr_d[11] v5 y5 ddr_d[10] u5 aa5 ddr_d[9] w4 w5 ddr_d[8] v4 ab4 i/o/z dv ddr2 ddr2 bi-directional data bus is configured as 16-bits wide. ddr_d[7] w3 w4 ddr_d[6] v3 ab3 ddr_d[5] u3 y3 ddr_d[4] v2 aa3 ddr_d[3] u2 aa2 ddr_d[2] u1 w2 ddr_d[1] t2 y2 ddr_d[0] t1 y1 ddr_vref t15 w18 i (3) reference voltage input for the sstl_18 i/o buffers ddr_vssdll t13 w15 gnd (3) ground for the ddr2 dll ddr_vdddll t12 w14 s (3) power (1.8 volts) for the ddr2 digital locked loop impedance control for ddr2 outputs. this must be connected via a ddr_zn t10 w12 (3) 200- w resistor to dv ddr2 . impedance control for ddr2 outputs. this must be connected via a ddr_zp t11 w13 (3) 200- w resistor to v ss . device overview 36 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-13. emac and mdio terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. emac ipd this pin is multiplexed between ethernet mac (emac) and gpio. mtxen/gp[75] d3 c4 i/o/z dv dd33 in ethernet mac mode, it is transmit enable input mtxen. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mtxclk/gp[73] a4 a4 i/o/z dv dd33 in ethernet mac mode, it is transmit clock input mtxclk. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mcol/gp[67] c6 c6 i/o/z dv dd33 in ethernet mac mode, it is collision detect input mcol. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mtxd3/gp[69] c5 a5 i/o/z dv dd33 in ethernet mac mode, it is transmit data 3 output mtxd3. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mtxd2/gp[70] d5 c5 i/o/z dv dd33 in ethernet mac mode, it is transmit data 2 output mtxd2. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mtxd1/gp[71] b4 b4 i/o/z dv dd33 in ethernet mac mode, it is transmit data 1 output mtxd1. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mtxd0/gp[72] d4 b5 i/o/z dv dd33 in ethernet mac mode, it is transmit data 0 output mtxd0. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mrxclk/gp[77] a3 a3 i/o/z dv dd33 in ethernet mac mode, it is receive clock input mrxclk. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mrxdv/gp[74] c4 d3 i/o/z dv dd33 in ethernet mac mode, it is receive data valid input mrxdv. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mrxer/gp[76] b3 b2 i/o/z dv dd33 in ethernet mac mode, it is receive error input mrxer. ipd this pin is multiplexed between ethernet mac (emac) and gpio. mcrs/gp[68] b5 b6 i/o/z dv dd33 in ethernet mac mode, it is carrier sense input mcrs. ipu this pin is multiplexed between ethernet mac (emac) and gpio. mrxd3/gp[82] c2 d2 i/o/z dv dd33 in ethernet mac mode, it is receive data 3 input mrxd3. ipu this pin is multiplexed between ethernet mac (emac) and gpio. mrxd2/gp[80] d2 c3 i/o/z dv dd33 in ethernet mac mode, it is receive data 2 input mrxd2. ipu this pin is multiplexed between ethernet mac (emac) and gpio. mrxd1/gp[79] b2 b3 i/o/z dv dd33 in ethernet mac mode, it is receive data 1 input mrxd1. ipu this pin is multiplexed between ethernet mac (emac) and gpio. mrxd0/gp[78] c3 c2 i/o/z dv dd33 in ethernet mac mode, it is receive data 0 input mrxd0. mdio this pin is multiplexed between mdio and gpio. ipu mdclk/gp[81] c1 d1 i/o/z in ethernet mac mode, it is management data clock output dv dd33 mdclk. ipu this pin is multiplexed between mdio and gpio. mdio/gp[83] d1 c1 i/o/z dv dd33 in ethernet mac mode, it is management data io mdio (i/o/z). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 37
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-14. vpfe terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. video/image in (vpfe) this pin is multiplexed between the vpfe (ccdc) and gpio. ipd in vpfe mode, this pin is the pixel clock input (pclk) used to load pclk/gp[54] a14 a18 i/o/z dv dd33 image data into the ccd controller (ccdc) on pins ci[7:0] and yi[7:0]. this pin is multiplexed between the vpfe (ccdc) and gpio. ipd in vpfe mode, this pin is the vertical synchronization signal (vd) that vd/gp[53] a13 a17 i/o/z dv dd33 can be either an input (slave mode) or an output (master mode), which signals the start of a new frame to the ccdc. this pin is multiplexed between the vpfe (ccdc) and gpio. ipd in vpfe mode, this pin is the horizontal synchronization signal (hd) hd/gp[52] a15 a19 i/o/z dv dd33 that can be either an input (slave mode) or an output (master mode), which signals the start of a new line to the ccdc. this pin is multiplexed between the vpfe (ccdc), emifa, and gpio. ci1(ccd9)/ ipd b12 c14 i/o/z this pin is ccdc input ci1 and it supports several modes: em_a[19]/gp[45] dv dd33 in 10-bit ccd raw mode, it is input ccd9. in 8-bit ycbcr mode, this pin should not be used. this pin is multiplexed between the vpfe (ccdc), emifa, and gpio. ci0(ccd8)/ ipd c12 c15 i/o/z this pin is ccdc input ci0 and it supports several modes: em_a[20]//gp[44] dv dd33 in 10-bit ccd raw mode, it is input ccd8. in 8-bit ycbcr mode, this pin should not be used. this pin is multiplexed between the vpfe (ccdc) and gpio. this pin is ccdc input yi7 and it supports several modes: yi7(ccd7)/ ipd a12 a15 i/o/z gp[43] dv dd33 in 10-bit ccd raw mode, it is input ccd7. in 8-bit ycbcr mode, it is time multiplexed between y7, cb7, and cr7 of the lower 8-bit channel. this pin is multiplexed between the vpfe (ccdc) and gpio. this pin is ccdc input yi6 and it supports several modes: yi6(ccd6)/ ipd b13 b15 i/o/z gp[42] dv dd33 in 10-bit ccd raw mode, it is input ccd6. in 8-bit ycbcr mode, it is time multiplexed between y6, cb6, and cr6 of the lower 8-bit channel. this pin is multiplexed between the vpfe (ccdc) and gpio. this pin is ccdc input yi5 and it supports several modes: yi5(ccd5)/ ipd c13 b16 i/o/z gp[41] dv dd33 in 10-bit ccd raw mode, it is input ccd5. in 8-bit ycbcr mode, it is time multiplexed between y5, cb5, and cr5 of the lower 8-bit channel. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal 38 device overview submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-14. vpfe terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. this pin is multiplexed between the vpfe(ccdc) and gpio. this pin is ccdc input yi4 and it supports several modes: yi4(ccd4)/ ipd d14 c18 i/o/z in 10-bit ccd raw mode, it is input ccd4. gp[40] dv dd33 in 8-bit ycbcr mode, it is time multiplexed between y4, cb4, and cr4 of the lower 8-bit channel. this pin is multiplexed between the vpfe (ccdc) and gpio. this pin is ccdc input yi3 and it supports several modes: yi3(ccd3)/ ipd b14 a16 i/o/z in 10-bit ccd raw mode, it is input ccd3. gp[39] dv dd33 in 8-bit ycbcr mode, it is time multiplexed between y3, cb3, and cr3 of the lower 8-bit channel. this pin is multiplexed between the vpfe (ccdc) and gpio. this pin is ccdc input yi2 and it supports several modes: yi2(ccd2)/ ipd c14 b17 i/o/z in 10-bit ccd raw mode, it is input ccd2. gp[38] dv dd33 in 8-bit ycbcr mode, it is time multiplexed between y2, cb2, and cr2 of the lower 8-bit channel. this pin is multiplexed between the vpfe (ccdc) and gpio. this pin is ccdc input yi1 and it supports several modes: yi1(ccd1)/ ipd b15 b18 i/o/z in 10-bit ccd raw mode, it is input ccd1. gp[37] dv dd33 in 8-bit ycbcr mode, it is time multiplexed between y1, cb1, and cr1 of the lower 8-bit channel. this pin is multiplexed between the vpfe (ccdc) and gpio. this pin is ccdc input yi0 and it supports several modes: yi0(ccd0)/ ipd c15 b19 i/o/z in 10-bit ccd raw mode, it is input ccd0. gp[36] dv dd3 in 8-bit ycbcr mode, it is time multiplexed between y0, cb0, and cr0 of the lower 8-bit channel. c_we/em_r/ w/ ipd this pin is multiplexed between vpfe (ccdc), emifa, and gpio. d13 c17 i/o/z gp[35] dv dd33 in vpfe mode, it is the ccd controller write enable input c_we. this pin is multiplexed between vpfe (ccdc), emifa, and gpio. c_field/em_a[21]/ ipd d12 c16 i/o/z in vpfe mode, it is ccdc field identification bidirectional signal gp[34] dv dd33 c_field. submit documentation feedback device overview 39
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-15. i2c terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. i2c for i2c, this pin is i2c clock. in i2c master mode, this pin is an output. in i2c slave mode, this pin is an input. scl m2 n2 i/o/z dv dd33 when the i2c module is used, for proper device operation, this pin must be pulled up via an external resistor. for i2c, this pin is the i2c bi-directional data signal. sda m3 p2 i/o/z dv dd33 when the i2c module is used, for proper device operation, this pin must be pulled up via an external resistor. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 40 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-16. multichannel buffered serial port 0 (mcbsp0) terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. multichannel buffered serial port 0 (mcbsp0) for more details on pin multiplexing, see section 3.7 , multiplexed pin configurations. clks0/tout0l/ ipd this pin is multiplexed between mcbsp0, timer0, and gpio. j4 l3 i/o/z gp[97] dv dd33 for mcbsp0, it is mcbsp0 external clock source (i). aclkr0/clkx0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. h1 j1 i/o/z gp[99] dv dd33 for mcbsp0, it is mcbsp0 transmit clock clkx0 (i/o/z). ahclkr0/clkr0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. j2 k1 i/o/z gp[101] dv dd33 for mcbsp0, it is mcbsp0 receive clock clkr0 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[2]/fsx0/ ipd h3 j2 i/o/z for mcbsp0, it is mcbsp0 transmit frame synchronization fsx0 gp[103] dv dd33 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[3]/fsr0/ ipd g4 j3 i/o/z for mcbsp0, it is mcbsp0 receive frame synchronization fsr0 gp[102] dv dd33 (i/o/z). axr0[1]/dx0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. j3 k2 i/o/z gp[104] dv dd33 for mcbsp0, it is mcbsp0 data transmit output dx0 (o/z). afsr0/dr0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. h4 k3 i/o/z gp[100] dv dd33 for mcbsp0, it is mcbsp0 data receive input dr0 (i). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 41
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-17. multichannel audio serial port (mcasp0) terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. mcasp0 amutein0/ ipd this pin is multiplexed between mcasp0 and gpio. f2 g3 i/o/z gp[109] dv dd33 for mcasp0, it is mcasp0 mute input amutein0 (i). ipd this pin is multiplexed between mcasp0 and gpio. amute0/gp[110] g3 h3 i/o/z dv dd33 for mcasp0, it is mcasp0 mute output amute0 (o/z). aclkr0/clkx0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. h1 j1 i/o/z gp[99] dv dd33 for mcasp0, it is mcasp0 receive bit clock aclkr0 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. ahclkr0/clkr0/ ipd j2 k1 i/o/z for mcasp0, it is mcasp0 receive high-frequency master clock gp[101] dv dd33 ahclkr0 (i/o/z). ipd this pin is multiplexed between mcasp0 and gpio. aclkx0/gp[106] f1 g1 i/o/z dv dd33 for mcasp0, it is mcasp0 transmit bit clock aclkx0 (i/o/z). this pin is multiplexed between mcasp0 and gpio. ipd ahclkx0/gp[108] g1 h1 i/o/z for mcasp0, it is mcasp0 transmit high-frequency master clock dv dd33 ahclkx0 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. afsr0/dr0/ ipd h4 k3 i/o/z for mcasp0, it is mcasp0 receive frame synchronization afsr0 gp[100] dv dd33 (i/o/z). this pin is multiplexed between mcasp0 and gpio. ipd afsx0/gp[107] g2 g2 i/o/z for mcasp0, it is mcasp0 transmit frame synchronization afsx0 dv dd33 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[3]/fsr0/ ipd g4 j3 i/o/z for mcasp0, it is mcasp0 transmit/receive (tx/rx) data pin 3 gp[102] dv dd33 axr0[3] (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[2]/fsx0/ ipd h3 j2 i/o/z for mcasp0, it is mcasp0 transmit/receive (tx/rx) data pin 2 gp[103] dv dd33 axr0[2] (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[1]/dx0/ ipd j3 k2 i/o/z for mcasp0, it is mcasp0 transmit/receive (tx/rx) data pin 1 gp[104] dv dd33 axr0[1] (i/o/z). this pin is multiplexed between mcasp0 and gpio. ipd axr0[0]/gp[105] h2 h2 i/o/z for mcasp0, it is mcasp0 transmit/receive (tx/rx) data pin 0 dv dd33 axr0[0] (i/o/z). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 42 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-18. high-end controller area network (hecc) signal type (1) other (2) (3) description zwt zdu name no. no. hecc hecc_rx/ ipu this pin is multiplexed between hecc, timer 1, and gpio. tinp1l/ l4 p3 i/o/z dv dd33 for hecc, this pin is hecc receive serial data hecc_rx ( i). gp[56] hecc_tx/ ipu this pin is multiplexed between hecc, timer 1, and gpio. tout1l/ k4 n3 i/o/z dv dd33 for hecc, this pin is hecc transmit serial data hecc_tx ( o/z). gp[55] (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 43
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-19. uart0 terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. uart0 urxd0/ ipu this pin is multiplexed between uart0 (data) and gpio. l2 m2 i/o/z gp[85] dv dd33 when used by uart0 this pin is the receive data input urxd0. utxd0/ ipu this pin is multiplexed between uart0 (data) and gpio. k3 n1 i/o/z gp[86] dv dd33 in uart0 mode, this pin is the transmit data output utxd0. ucts0 ipu this pin is multiplexed between the uart0 (flow control) and gpio. l1 p1 i/o/z gp[87] dv dd33 in uart0 mode, this pin is the clear to send input ucts0. urts0 this pin is multiplexed between the uart0 (flow control), pwm0, ipu pwm0 l3 m3 i/o/z and gpio. dv dd33 gp[88] in uart0 mode, this pin is the ready to send output urts0. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 44 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-20. pwm0, pwm1, and pwm2 terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. pwm2 this pin is multiplexed between the system clock generator (pll1), clkout0/pwm2/ ipd m1 r1 i/o/z pwm2, and gpio. gp[84] dv dd33 for pwm2, this pin is output pwm2. pwm1 ipd this pin is multiplexed between gpio and pwm1. gp[4]/pwm1 f3 f3 i/o/z dv dd33 for pwm1, this pin is output pwm1. pwm0 this pin is multiplexed between the uart0 (flow control), pwm0, urts0/pwm0/ ipu l3 m3 i/o/z and gpio. gp[88] dv dd33 for pwm0, this pin is output pwm0. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 45
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-21. timer 0, timer 1, and timer 2 terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. timer 2 no external pins. the timer 2 (watchdog) peripheral pins are not pinned out as external pins. timer 1 hecc_rx/ this pin is multiplexed between the hecc, timer 1, and gpio. ipu tinp1l/ l4 p3 i/o/z for timer 1, this pin is the timer 1 input pin for the lower 32-bit dv dd33 gp[56] counter hecc_tx/ this pin is multiplexed between the hecc, timer 1, and gpio. ipu tout1l/ k4 n3 i/o/z for timer 1, this pin is the timer 1 output pin for the lower 32-bit dv dd33 gp[55] counter timer 0 this pin is multiplexed between the timer 0 and gpio. tinp0l/ ipd k2 l2 i/o/z for timer 0, this pin is the timer 0 input pin for the lower 32-bit gp[98] dv dd33 counter clks0/ this pin is multiplexed between the mcbsp0, timer 0, and gpio. ipd tout0l/ j4 l3 i/o/z for timer 0, this pin is the timer 0 output pin for the lower 32-bit dv dd33 gp[97] counter (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 46 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-22. gpio terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. gpio 87 out of 111 gpio pins on the dm6431 device are multiplexed with other peripherals pin functions (e.g., vpfe, emac/mdio, mcasp0, mcbsp0, timer 0, timer 1, uart0, pwm0, pwm1, pwm2, emifa, and the clkout0 pin), see the peripheral-specific terminal functions tables for the gpio multiplexing. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 47
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-23. standalone gpio 3.3 v terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. standalone gpio 3.3 v ipd gp[0] e1 e1 i/o/z this pin functions as standalone gpio pin 0. dv dd33 ipd gp[1] e2 e2 i/o/z this pin functions as standalone gpio pin 1. dv dd33 ipd gp[2] e3 f1 i/o/z this pin functions as standalone gpio pin 2. dv dd33 ipd gp[3] e4 f2 i/o/z this pin functions as standalone gpio pin 3. dv dd33 gp[22]/ ipd f18 j20 i/o/z (bootmode0) dv dd33 gp[23]/ ipd f15 k20 i/o/z (bootmode1) dv dd33 gp[24]/ ipd these pins function as boot configuration pins during device reset. g15 l20 i/o/z (bootmode2) dv dd33 after device reset, these pins function as standalone gpio. gp[25]/ ipd g16 h21 i/o/z (bootmode3) dv dd33 gp[26]/ ipd g17 k19 i/o/z (fastboot) dv dd33 for proper dm6431 device operation, this pin must be pulled up via ipu gp[27] h17 l19 i/o/z an external resistor. dv dd33 after device reset, this pin functions as standalone gpio pin 27. for proper dm6431 device operation, this pin must be pulled down ipd gp[28] h16 j21 i/o/z via an external resistor. dv dd33 after device reset, this pin functions as standalone gpio pin 28. ipd gp[29] h15 k21 i/o/z this pin functions as standalone gpio pin 29. dv dd33 ipd gp[30] g19 k22 i/o/z this pin functions as standalone gpio pin 30. dv dd33 ipd gp[31] d19 g22 i/o/z this pin functions as standalone gpio pin 31. dv dd33 ipu gp[57] a7 a8 i/o/z this pin functions as standalone gpio pin 57. dv dd33 ipu gp[58] c8 b9 i/o/z this pin functions as standalone gpio pin 58. dv dd33 ipd gp[59] d7 c9 i/o/z this pin functions as standalone gpio pin 59. dv dd33 ipd gp[60] a8 a9 i/o/z this pin functions as standalone gpio pin 60. dv dd33 ipd gp[61] b7 b8 i/o/z this pin functions as standalone gpio pin 61. dv dd33 ipd gp[62] c7 c8 i/o/z this pin functions as standalone gpio pin 62. dv dd33 ipd gp[63] a6 a7 i/o/z this pin functions as standalone gpio pin 63. dv dd33 ipd gp[64] d6 c7 i/o/z this pin functions as standalone gpio pin 64. dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal 48 device overview submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-23. standalone gpio 3.3 v terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. ipd gp[65] b6 b7 i/o/z this pin functions as standalone gpio pin 65. dv dd33 ipd gp[66] a5 a6 i/o/z this pin functions as standalone gpio pin 66. dv dd33 submit documentation feedback device overview 49
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-24. reserved terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. reserved rsv1 e5 d4 reserved. (leave unconnected, do not connect to power or ground) rsv2 k5 l4 reserved. (leave unconnected, do not connect to power or ground) rsv3 l5 m4 reserved. (leave unconnected, do not connect to power or ground) rsv4 l15 p19 reserved. (leave unconnected, do not connect to power or ground) rsv5 r13 w16 reserved. (leave unconnected, do not connect to power or ground) reserved. this pin must be tied directly to v ss for normal device rsv6 n19 v22 operation. rsv7 p19 v21 reserved. (leave unconnected, do not connect to power or ground) rsv8 p18 u22 reserved. (leave unconnected, do not connect to power or ground) rsv9 n18 t21 reserved. (leave unconnected, do not connect to power or ground) rsv10 n17 t22 reserved. (leave unconnected, do not connect to power or ground) reserved. this pin must be tied directly to v ss for normal device rsv11 p16 u20 operation. reserved. this pin must be tied directly to v ss for normal device rsv12 p17 v20 operation. reserved. this pin must be tied directly to v ss for normal device rsv13 n15 t20 operation. reserved. this pin must be tied directly to v ss for normal device rsv14 p15 t19 operation. reserved. this pin must be tied directly to v ss for normal device rsv15 n16 u21 operation. ipd reserved. for proper dm6431 device operation, this pin must be rsv16 t3 w3 i dv dd33 pulled down via an external resistor and tied to v ss . ipd rsv17 e10 d12 i/o/z reserved. (leave unconnected, do not connect to power or ground) dv dd33 ipd rsv18 e11 d13 i/o/z reserved. (leave unconnected, do not connect to power or ground) dv dd33 ipd rsv19 e12 d14 i/o/z reserved. (leave unconnected, do not connect to power or ground) dv dd33 rsv20 t14 y15 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv21 t16 y18 i/o/z reserved. (leave unconnected, do not connect to power or ground) reserved. for proper dm6431 device operation, this pin must be rsv22 u14 aa15 i/o/z pulled down via an external 1-k w resistor. reserved. for proper dm6431 device operation, this pin must be rsv23 u16 aa18 i/o/z pulled down via an external 1-k w resistor. rsv24 w14 aa16 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv25 v14 y16 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv26 w15 ab16 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv27 v15 aa17 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv28 u15 y17 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv29 w16 ab17 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv30 v16 ab18 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv31 t17 aa19 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv32 v17 y19 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv33 u17 ab19 i/o/z reserved. (leave unconnected, do not connect to power or ground) (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 50 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-24. reserved terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. rsv34 t18 aa20 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv35 w17 y20 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv36 u18 ab20 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv37 v18 y21 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv38 u19 aa21 i/o/z reserved. (leave unconnected, do not connect to power or ground) rsv39 t19 y22 i/o/z reserved. (leave unconnected, do not connect to power or ground) submit documentation feedback device overview 51
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-25. supply terminal functions signal type (1) other description zwt zdu name no. no. supply voltage pins a1 a2 a2 a21 a18 b1 e6 d6 e8 d8 f5 d10 f7 d16 f9 d18 f11 e3 f13 e5 g6 e7 g8 e9 g10 e11 g12 e13 g14 e15 h5 e17 h18 e19 j1 f4 j6 f18 j14 g5 3.3 v i/o supply voltage dv dd33 s (see the power-supply decoupling section of this data manual) j16 g19 k15 h4 k17 h18 l6 j5 m5 j19 m15 k4 n6 k18 p1 l1 l5 l21 m18 m20 n5 n19 p4 p18 p20 p22 r5 t4 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal device overview 52 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-25. supply terminal functions (continued) signal type (1) other description zwt zdu name no. no. l14 u5 p5 v1 p7 v4 p9 v6 p11 v8 p13 v10 r4 v12 r6 v14 r8 v16 1.8 v ddr2 i/o supply voltage dv ddr2 s (see the power-supply decoupling section of this data manual) r10 v18 r12 w7 r14 w9 r16 w11 t5 w17 v1 w19 w18 aa1 w19 ab21 ab22 h7 j10 h9 j11 h11 j12 h13 j13 j8 k9 j10 k14 j12 l9 k7 l13 k9 l14 k11 m9 1.2 v core supply voltage (-3/-3q/-3s devices) cv dd k13 m10 s (see the power-supply decoupling section of this data manual) l8 m14 l10 n9 l12 n14 m7 p10 m9 p11 m11 p12 m13 p13 n8 n10 n12 submit documentation feedback device overview 53
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 2-26. ground terminal functions signal type (1) other description zwt zdu name no. no. ground pins a19 a1 b1 a22 b19 b22 e7 d5 e9 d7 e13 d9 f4 d11 f6 d15 f8 d17 f10 e4 f12 e6 f14 e8 g5 e10 g7 e12 g9 e14 g11 e16 g13 e18 g18 f5 h6 f19 v ss h8 g4 gnd ground pins h10 g18 h12 h5 h14 h19 h19 j4 j5 j9 j7 j14 j9 j18 j11 k5 j13 k10 j15 k11 j17 k12 j18 k13 k1 l10 k6 l11 k8 l12 k10 l18 k12 l22 k14 m1 k16 m5 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal 54 device overview submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 2-26. ground terminal functions (continued) signal type (1) other description zwt zdu name no. no. l7 m11 l9 m12 l11 m13 l13 m19 l17 n4 l19 n10 m6 n11 m8 n12 m10 n13 m12 n18 m14 p5 m16 p9 m17 p14 m18 p21 m19 r4 n5 r18 n7 r19 n9 r20 n11 r21 n13 r22 n14 t5 v ss p6 t18 gnd ground pins p8 u4 p10 u18 p12 u19 p14 v5 r1 v7 r5 v9 r7 v11 r9 v13 r11 v15 r15 v17 r17 v19 r18 w1 r19 w6 v19 w8 w1 w10 w2 w20 w21 w22 aa22 ab1 ab2 submit documentation feedback device overview 55
2.7 device support 2.7.1 development support 2.8 device and development-support tool nomenclature tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com ti offers an extensive line of development tools for the tms320dm643x dmp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the tool's support documentation is electronically available within the code composer studio? integrated development environment (ide). the following products support development of tms320dm643x dmp-based applications: software development tools: code composer studio? integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp/bios?), which provides the basic run-time target software needed to support any soc application. hardware development tools: extended development system (xds?) emulator (supports tms320dm643x dmp multiprocessor system debug) evm (evaluation module) for a complete listing of development-support tools for the tms320dm643x dmp platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all dsp devices and support tools. each dsp commercial family member has one of three prefixes: tmx, tmp, or tms (e.g., tms320dm6431zwtq3). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device's electrical specifications. tmp final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. tms fully-qualified production device. support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product. tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. device overview 56 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, zwt), the temperature range (for example, "blank" is the commercial temperature range), and the device speed range in megahertz (for example, "3" indicates [300-mhz]). figure 2-10 provides a legend for reading the complete device name for any tms320dm643x dmp platform member. figure 2-10. device nomenclature submit documentation feedback device overview 57 c64x+? dsp: dm6437dm6435 dm6433 dm6431 prefix tmx 320 dm6431 zwt tmx = experimental devicetms = qualified device device family 320 = tms320? dsp family package type(a) zwt = 361-pin plastic bga, with pb-free soldered balls zdu = 376-pin plastic bga, with pb-free soldered balls [green] device a. bga = ball grid array b. for tmx initial devices, the device number is dm6437. device speed range ( ) 3 = 300 mhz temperature range (junction) ( ) ( ) silicon revision: blank = revision 1.3 blank = 0 c to 90 c, commercial grade q = -40c to 125c, automotive grade r = 0 c to 90 c, commercial grade (tape and reel) s = -40c to 125c, automotive grade (tape and reel)
2.9 documentation support 2.9.1 related documentation from texas instruments tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the following documents describe the tms320dm643x digital media processor (dmp). copies of these documents are available on the internet at www.ti.com . tip: enter the literature number in the search box provided at www.ti.com. the current documentation that describes the dm643x dmp, related peripherals, and other technical collateral, is available in the c6000 dsp product folder at: www.ti.com/c6000 . spru978 tms320dm643x dmp dsp subsystem reference guide. describes the digital signal processor (dsp) subsystem in the tms320dm643x digital media processor (dmp). spru983 tms320dm643x dmp peripherals overview reference guide. provides an overview and briefly describes the peripherals available on the tms320dm643x digital media processor (dmp). spraa84 tms320c64x to tms320c64x+ cpu migration guide. describes migrating from the texas instruments tms320c64x digital signal processor (dsp) to the tms320c64x+ dsp. the objective of this document is to indicate differences between the two cores. functionality in the devices that is identical is not included. spru732 tms320c64x/c64x+ dsp cpu and instruction set reference guide. describes the cpu architecture, pipeline, instruction set, and interrupts for the tms320c64x and tms320c64x+ digital signal processors (dsps) of the tms320c6000 dsp family. the c64x/c64x+ dsp generation comprises fixed-point devices in the c6000 dsp platform. the c64x+ dsp is an enhancement of the c64x dsp with added functionality and an expanded instruction set. spru871 tms320c64x+ dsp megamodule reference guide. describes the tms320c64x+ digital signal processor (dsp) megamodule. included is a discussion on the internal direct memory access (idma) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. device overview 58 submit documentation feedback
3 device configurations 3.1 system module registers tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the system module includes status and control registers required for configuration of the device. brief descriptions of the various registers are shown in table 3-1 . system module registers required for device configurations are discussed in the following sections. table 3-1. system module register memory map hex address range register acronym description 0x01c4 0000 pinmux0 pin multiplexing control 0 (see section 3.7.2.1 , pinmux0 register description). 0x01c4 0004 pinmux1 pin multiplexing control 1 (see section 3.7.2.2 , pinmux1 register description). 0x01c4 0008 dspbootaddr dsp boot address (see section 3.4.2.3 , dspbootaddr register). 0x01c4 000c bootcomplt boot complete (see section 3.4.2.2 , bootcmplt register). 0x01c4 0010 ? reserved 0x01c4 0014 bootcfg device boot configuration (see section 3.4.2.1 , bootcfg register). 0x01c4 0018 - 0x01c4 0027 ? reserved 0x01c4 0028 jtagid jtag id (see section 6.21.1 , jtag id (jtagid) register description(s)). 0x01c4 002c ? reserved 0x01c4 0030 ? reserved 0x01c4 0034 ? reserved 0x01c4 0038 ? reserved 0x01c4 003c mstpri0 bus master priority control 0 (see section 3.6.1 , switch central resource (scr) bus priorities). 0x01c4 0040 mstpri1 bus master priority control 1 (see section 3.6.1 , switch central resource (scr) bus priorities). 0x01c4 0044 vpss_clkctl vpss clock control (see section 3.3.2 , vpss clocks). 0x01c4 0048 vdd3p3v_pwdn v dd 3.3-v i/o powerdown control (see section 3.2 , power considerations). 0x01c4 004c ddrvtper ddr2 vtp enable register (see section 6.9.4 , ddr2 memory controller). 0x01c4 0050 - 0x01c4 0080 ? reserved 0x01c4 0084 timerctl timer control (see section 3.6.2.1 , timer control register). 0x01c4 0088 edmatccfg edma transfer controller default burst size configuration (see section 3.6.2.2 , edma tc configuration register). 0x01c4 008c ? reserved submit documentation feedback device configurations 59
3.2 power considerations tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the dm6431 provides several means of managing power consumption. as described in the section 6.3.4 , dm6431 power and clock domains, the dm6431 has one single power domain?the ?always on? power domain. within this power domain, the dm6431 utilizes local clock gating via the power and sleep controller (psc) to achieve power savings. for more details on the psc, see section 6.3.5 , power and sleep controller (psc) and the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). some of the dm6431 peripherals support additional power saving features. for more details on power saving features supported, see the tms320dm643x dmp peripherals overview reference guide (literature number spru983 ). most dm6431 3.3-v i/os can be powered-down to reduce power consumption. the vdd3p3v_pwdn register in the system module (see figure 3-1 ) is used to selectively power down unused 3.3-v i/o pins. for independent control, the 3.3-v i/os are separated into functional groups?most of which are named according to the pin multiplexing groups (see table 3-2 ). only the i/o buffers in these groups are powered up by default: clkout block, emifa/vpss block, host block, and gpio block. note: to save power, all other i/o buffers are powered down by default. before using these pins, the user must program the vdd3p3v_pwdn register to power up the corresponding i/o buffers. for a list of multiplexed pins on the device and the pin mux group each pin belongs to, see section 3.7.3.1 , multiplexed pins on dm6431. 31 16 reserved r-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rsv embk3 ur0fc ur0dat timer1 timer0 sp pwm1 gpio host embk2 embk1 embk0 clkout r-00 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 3-1. vdd3p3v_pwdn register? 0x01c4 0048 table 3-2. vdd3p3v_pwdn register bit descriptions (1) bit name description 31:14 reserved reserved. read-only, writes have no effect. reserved. this bit should be programmed to 1 during device initialization (see section 3.8 , 13 rsv device initialization sequence after reset). emifa/vpss sub-block 3 i/o power down control. controls the power of the 8 i/o pins in the emifa/vpss sub-block 3. 12 embk3 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). uart0 flow control block i/o power down control. controls the power of the 2 i/o pins in the uart0 flow control block. 11 ur0fc 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. (1) for more details on i/o pins belonging to each pin mux block, see section 3.7 , multiplexed pin configurations. device configurations 60 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-2. vdd3p3v_pwdn register bit descriptions (continued) bit name description uart0 data block i/o power down control. controls the power of the 2 i/o pins in the uart0 data block. 10 ur0dat 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. timer1 block i/o power down control. controls the power of the 2 i/o pins in the timer1 block. 9 timer1 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. timer0 block i/o power down control. controls the power of the 2 i/o pins in the timer0 block. 8 timer0 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. serial port block i/o power down control. controls the power of the 12 i/o pins in the serial port block (serial port sub-block 0 and serial port sub-block 1). 7 sp 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. pwm1 block i/o power down control. contros thel power of the 1 i/o pin in the pwm1 block. 6 pwm1 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. gpio block i/o power down control. controls the power of the 4 i/o pins in the gpio block (gp[3:0]). note: the gpio block contains standalone gpio pins and is not a pin mux group. 5 gpio 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). host block i/o power down control. controls the power of the 27 i/o pins in the host block. 4 host 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). emifa/vpss sub-block 2 i/o power down control. controls the power of the 3 i/o pins in the emifa/vpss sub-block 2. 3 embk2 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). emifa/vpss sub-block 1 i/o power down control. controls the power of the 29 i/o pins in the emifa/vpss sub-block 1. 2 embk1 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). emifa/vpss sub-block 0 i/o power down control. controls the power of the 21 i/o pins in the emifa/vpss sub-block 0. 1 embk0 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). clkout block i/o power down control. controls the power of the 1 i/o pin in the clkout block. 0 clkout 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). submit documentation feedback device configurations 61
3.3 clock considerations 3.3.1 clock configurations after device reset 3.3.1.1 device clock frequency 3.3.1.2 module clock state tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com global device and local peripheral clocks are controlled by the pll controllers (pllc1 and pllc2) and the power and sleep controller (psc). in addition, the system module vpss_clkctl register configures the clock source to the video processing subsystem (vpss). after device reset, the user is responsible for programming the pll controllers (pllc1 and pllc2) and the power and sleep controller (psc) to bring the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not). for additional power savings, some of the dm6431 peripherals support clock gating within the peripheral boundary. for more details on clock gating and power saving features supported by a specific peripheral, see the peripheral-specific reference guides [listed/linked in the tms320dm643x dmp peripherals overview reference guide (literature number spru983 )]. the dm6431 defaults to pll bypass mode. to bring the device up to the desired clock frequency, the user should program pllc1 and pllc2 after device reset. dm6431 supports a fastboot option, where upon exit from device reset the internal bootloader code automatically programs the pllc1 into pll mode with a specific pll multiplier and divider to speed up device boot. while the fastboot option is beneficial for faster boot, the pll multiplier and divider selected for boot may not be the exact frequency desired for the run-time application. it is the user's responsibility to reconfigure pllc1 after fastboot to bring the device into the desired clock frequency. section 3.4.1 , boot modes discusses the different fast boot modes in more detail. the user must adhere to the various clock requirements when programming the pllc1 and pllc2: fixed frequency ratio requirements between clkdiv1, clkdiv3, and clkdiv6 clock domains. for more details on the frequency ratio requirements, see section 6.3.4 , dm6431 power and clock domains. pll multiplier and frequency ranges. for more details on pll multiplier and frequency ranges, see section 6.7.1 , pll1 and pll2. the clock and reset state for each of the modules is controlled by the power and sleep controller (psc). table 3-3 shows the default state of each module after a device-level global reset. the dm6431 device has four different module states?enable, disable, syncreset, or swrstdisable. for more information on the definitions of the module states, the psc, and psc programming, see section 6.3.5 , power and sleep controller (psc) and the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). table 3-3. dm6431 default module states default module state lpsc # module name [psc register mdstatn.state] 0 vpss (master) swrstdisable 1 vpss (slave) swrstdisable 2 edmacc swrstdisable 3 edmatc0 swrstdisable 4 edmatc1 swrstdisable 5 edmatc2 swrstdisable 6 emac memory controller swrstdisable 7 mdio swrstdisable 8 emac swrstdisable 9 mcasp0 swrstdisable device configurations 62 submit documentation feedback
3.3.2 vpss clocks 3.4 boot sequence tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-3. dm6431 default module states (continued) default module state lpsc # module name [psc register mdstatn.state] 13 ddr2 memory contoller swrstdisable swrstdisable, if configuration pins aem[2:0] = 000b 14 emifa enable, if configuration pins aem[2:0] = others [001b and 101b] 16 mcbsp0 swrstdisable 18 i2c swrstdisable 19 uart0 swrstdisable 22 hecc swrstdisable 23 pwm0 swrstdisable 24 pwm1 swrstdisable 25 pwm2 swrstdisable 26 gpio swrstdisable 27 timer0 swrstdisable 28 timer1 swrstdisable 39 c64x+ cpu enable the video processing subsystem (vpss) clocks are controlled via the vpss_clkctl register. the vpss_clkctl register format is shown in figure 3-2 and the bit field descriptions are given in table 3-4 . 31 16 reserved r-0000 0000 0000 0000 15 5 4 3 2 1 0 pclk reserved reserved reserved inv r-0000 0000 000 r/w-00 r/w-0 r/w-00 legend: r = read; w = write; - n = value after reset figure 3-2. vpss_clkctl register? 0x01c4 0044 table 3-4. vpss_clkctl register description bit name description 31:5 reserved reserved. read-only, writes have no effect. reserved. for proper device operation, the user must only write "0" to these 4:3 reserved bits. pclk polarity 2 pclkinv 0 = vpss receives normal pclk [ default]. 1 = vpss receives inverted pclk. reserved. for proper device operation, the user must only write "0" to these 1:0 reserved bits. the boot sequence is a process by which the device's memory is loaded with program and data sections, and by which some of the device's internal registers are programmed with predetermined values. the boot sequence is started automatically after each device-level global reset. for more details on device-level global resets, see section 6.5 , reset. submit documentation feedback device configurations 63
3.4.1 boot modes tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com there are several methods by which the memory and register initialization can take place. each of these methods is referred to as a boot mode. the boot mode to be used is selected at reset. for more information on the bootmode selections, see section 3.4.1 , boot modes. the device is booted through multiple means?primary bootloaders within internal rom or emifa, and secondary user bootloaders from peripherals or external memories. boot modes, pin configurations, and register configurations required for booting the device, are described in the following subsections. the dm6431 boot modes are determined by these device boot and configuration pins. for information on how these pins are sampled at device reset, see section 6.5.1.2 , latching boot and configuration pins. bootmode[3:0] fastboot aem[2:0] pllms[2:0] note: the pllms[2:0] configuration pins are actually multiplexed with the aeaw[2:0] configuration pins. for more details on the multiplexed aeaw[2:0]/pllms[2:0] configuration pins and control, see section 3.5.1.2 , emifa address width selects (aeaw[2:0]) and fastboot pll multiplier selects (pllms[2:0]). bootmode[3:0] determines the type of boot (e.g., i2c boot or emifa boot, etc.). fastboot determines if the pll is enabled during boot to speed up the boot process. the combination of aem[2:0] and pllms[2:0] is used by bootloader code to determine the pll multiplier used during fastboot modes (fastboot = 1). the dm6431 boot modes are grouped into three categories?non-fastboot modes, fixed-multiplier fastboot modes, and user-select multiplier fastboot modes. non-fastboot modes (fastboot = 0): the device operates in default pll bypass mode during boot. the non-fastboot bootmodes available on the dm6431 are shown in table 3-5 . fixed-multiplier fastboot modes (fastboot = 1, aem[2:0] = 001b): the bootloader code speeds up the device during boot according to the fixed pll multipliers. the fixed-multiplier fastboot bootmodes available on the dm6431 are shown in table 3-6 . note: the pllms[2:0] configurations have no effect on the fixed-multiplier fastboot modes, as these pins function as aeaw[2:0] to select the emifa address width when aem[2:0] = 001b. user-select multiplier fastboot modes (fastboot = 1, aem[2:0] = 000b and 101b): the bootloader code speeds up the device during boot. the pll multiplier is selected by the user via the pllms[2:0] pins. the user-select multiplier fastboot bootmodes available on the dm6431 are shown in table 3-7 . all other modes not shown in these tables are reserved and invalid settings. for more information on how these pins are sampled at device reset, see section 6.5.1.2 , latching boot and configuration pins. device configurations 64 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-5. non-fastboot modes (fastboot = 0) device boot and configuration pllc1 clock setting at boot pins dm6431 dmp dspbootaddr boot description (1) (master/slave) (default) (1) device pll clkdiv1 domain bootmode[3:0] frequency mode (2) (sysclk1 divider) (sysclk1) 0000 no boot (emulation boot) master bypass /1 clkin 0x0010 0000 0001 reserved ? ? ? ? ? 0010 reserved ? ? ? ? ? 0011 reserved ? ? ? ? ? emifa rom direct boot 0100 master bypass /1 clkin 0x4200 000 [pll bypass mode] i2c boot 0101 master bypass /1 clkin 0x0010 0000 [standard mode] (3) 0110 16-bit spi boot [mcbsp0] master bypass /1 clkin 0x0010 0000 0111 nand flash boot master bypass /1 clkin 0x0010 0000 uart boot without 1000 hardware flow control master bypass /1 clkin 0x0010 0000 [uart0] 1001 reserved ? ? ? ? ? 1010 reserved ? ? ? ? ? 1011 reserved ? ? ? ? ? 1100 reserved ? ? ? ? ? 1101 reserved ? ? ? ? ? uart boot with hardware 1110 master bypass /1 clkin 0x0010 0000 flow control [uart0] 24-bit spi boot (mcbsp0 + 1111 master bypass /1 clkin 0x0010 0000 gp[97]) (1) for all boot modes that default to dspbootaddr = 0x0010 0000 (i.e., all boot modes except the emifa rom direct boot, bootmode[3:0] = 0100, fastboot = 0), the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram. if cache use is required, the application code must explicitly enable the cache. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). (2) the pll mode for non-fastboot modes is fixed as shown in this table; therefore, the pllms[2:0] configuration pins have no effect on the pll mode. (3) i2c boot (bootmode[3:0] = 0101b) is only available if the mxi/clkin frequency is between 21 mhz to 30 mhz. i2c boot is not available for mxi/clkin frequencies less than 21 mhz. submit documentation feedback device configurations 65
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-6. fixed-multiplier fastboot modes (fastboot = 1, aem[2:0] = 001b) device boot and configuration pllc1 clock setting at boot pins dm6431 dmp dspbootaddr boot description (1) (master/slave) (default) (1) device pll clkdiv1 domain bootmode[3:0] frequency mode (2) (sysclk1 divider) (sysclk1) 0000 no boot (emulation boot) master bypass /1 clkin 0x0010 0000 0001 reserved ? ? ? ? ? 0010 reserved ? ? ? ? ? 0011 reserved ? ? ? ? ? emifa rom fastboot 0100 with application image master x20 /2 clkin x20 / 2 0x0010 000 script (ais) i2c boot 0101 master x20 /2 clkin x20 / 2 0x0010 0000 [fast mode] (3) 0110 16-bit spi boot [mcbsp0] master x20 /2 clkin x20 / 2 0x0010 0000 0111 nand flash boot master x20 /2 clkin x20 / 2 0x0010 0000 uart boot without 1000 hardware flow control master x20 /2 clkin x20 / 2 0x0010 0000 [uart0] emifa rom fastboot 1001 master x20 /2 clkin x20 / 2 0x0010 0000 without ais 1010 reserved ? ? ? ? ? 1011 reserved ? ? ? ? ? 1100 reserved ? ? ? ? ? 1101 reserved ? ? ? ? ? uart boot with hardware 1110 master x20 /2 clkin x20 / 2 0x0010 0000 flow control [uart0] 24-bit spi boot (mcbsp0 + 1111 master x20 /2 clkin x20 / 2 0x0010 0000 gp[97]) (1) for all boot modes that default to dspbootaddr = 0x0010 0000, the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram. if cache use is required, the application code must explicitly enable the cache. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). (2) the pll mode for fixed-multiplier fastboot modes is fixed as shown in this table; therefore, the pllms[2:0] configuration pins have no effect on the pll mode. (3) i2c boot (bootmode[3:0] = 0101b) is only available if the mxi/clkin frequency is between 21 mhz to 30 mhz. i2c boot is not available for mxi/clkin frequencies less than 21 mhz. 66 device configurations submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-7. user-select multiplier fastboot modes (fastboot = 1, aem[2:0] = 000b or 101b) device boot and configuration pllc1 clock setting at boot pins dm6431 dmp dspbootaddr boot description (1) (master/slave) (default) (1) device pll clkdiv1 domain bootmode[3:0] frequency mode (2) (sysclk1 divider) (sysclk1) 0000 no boot (emulation boot) master bypass /1 clkin 0x0010 0000 0001 reserved ? ? ? ? ? 0010 reserved ? ? ? ? ? 0011 reserved ? ? ? ? ? emifa rom fastboot 0100 master table 3-8 /2 table 3-8 0x0010 0000 with ais i2c boot 0101 master table 3-8 /2 table 3-8 0x0010 0000 [fast mode] (3) 0110 16-bit spi boot [mcbsp0] master table 3-8 /2 table 3-8 0x0010 0000 0111 nand flash boot master table 3-8 /2 table 3-8 0x0010 0000 uart boot without 1000 hardware flow control master table 3-8 /2 table 3-8 0x0010 0000 [uart0] emifa rom fastboot 1001 master table 3-8 /2 table 3-8 ? without ais 1010 reserved ? ? ? ? ? 1011 reserved ? ? ? ? ? 1100 reserved ? ? ? ? ? 1101 reserved ? ? ? ? ? uart boot with hardware 1110 master table 3-8 /2 table 3-8 0x0010 0000 flow control [uart0] 1111 reserved ? ? ? ? ? (1) for all boot modes that default to dspbootaddr = 0x0010 0000, the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram. if cache use is required, the application code must explicitly enable the cache. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). (2) any supported pll mode is available. [see table 3-8 for supported dm6431 pll mode options]. (3) i2c boot (bootmode[3:0] = 0101b) is only available if the mxi/clkin frequency is between 21 mhz to 30 mhz. i2c boot is not available for mxi/clkin frequencies less than 21 mhz. table 3-8. pll multiplier selection (pllms[2:0]) in user-select multiplier fastboot modes (fastboot = 1; aem[2:0] = 000b or 101b) device boot and pllc1 clock setting at boot configuration pins clkdiv1 domain pllms[2:0] pll mode device frequency (sysclk1) (sysclk1 divider) 000 x20 /2 clkin x20 / 2 001 x15 /2 clkin x15 / 2 010 x16 /2 clkin x16 / 2 011 x18 /2 clkin x18 / 2 100 x22 /2 clkin x22 / 2 101 x25 /2 clkin x25 / 2 110 x27 /2 clkin x27 / 2 111 x30 /2 clkin x30 / 2 submit documentation feedback device configurations 67
3.4.1.1 fastboot tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com as shown in table 3-5 , table 3-6 , and table 3-7 , at device reset the boot controller defaults the dspbootaddr to one of two values based on the boot mode selected. in all boot modes, the c64x+ is immediately released from reset and begins executing from address location indicated in dspbootaddr. internal bootloader rom (0x0010 0000): for most boot modes, the dspbootaddr defaults to the internal bootloader rom so that the dsp can immediately execute the bootloader code in the internal rom. the bootloader code decodes the captured bootmode, fastboot, default aem (daem), and pllms information (in the bootcfg register) to determine the proper boot operation. note: for all boot modes that default to dspbootaddr = 0x0010 0000, the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram. if cache use is required, the application code must explicitly enable the cache. for more information on boot modes, see section 3.4.1 , boot modes. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). emifa chip select space 2 (0x4200 0000): the emifa rom direct boot in pll bypass mode (bootcfg settings bootmode[3:0] = 0100b, fastboot = 0) is the only exception where the dspbootaddr defaults to the emifa chip select space 2. the dsp begins execution directly from the external rom at this emifa space. for more information how the bootloader code handles each boot mode, see using the tms320dm643x bootloader application report (literature number spraag0 ). when dm6431 exits pin reset ( reset or por released), the pll controllers (pllc1 and pllc2) default to pll bypass mode. this means the plls are disabled, and the mxi/clkin clock input is driving the chip. all the clock domain divider ratios discussed in section 6.3.4 , dm6431 power and clock domains, still apply. for example, assume an mxi/clkin frequency of 27 mhz?meaning the internal clock source for emifa is at clkdiv3 domain = 27 mhz/3 = 9 mhz, a very slow clock. in addition, the emifa registers are reset to the slowest configuration which translates to very slow peripheral operation/boot. to optimize boot time, the user should reprogram clock settings via the pllc as early as possible during the boot process. the fastboot pin facilitates this operation by allowing the device to boot at a faster clock rate. except for the emifa rom direct boot in pll bypass mode (bootcfg settings bootmode[3:0] = 0100b, fastboot = 0), all other boot modes default to executing from the internal bootloader rom. the first action that the bootloader code takes is to decode the boot mode. if the fastboot option is selected (bootcfg.fastboot = 1), the bootloader software begins by programming the pllc1 (system pllc) to pll mode to give the device a slightly faster operation before fetching code from external devices. the exact pll multiplier that the bootloader uses is determined by the aem[2:0] and pllms[2:0] settings, as shown in table 3-6 and table 3-7 . some boot modes must be accompanied with fastboot = 1 so that the corresponding peripheral can run at a reasonable rate to communicate to the external device(s). note: pllc2 still stays in pll bypass mode, the bootloader does not reconfigure it. device configurations 68 submit documentation feedback
3.4.1.2 selecting fastboot pll multiplier 3.4.1.3 emifa boot modes tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-6 , table 3-7 , and table 3-8 show the pll multipliers used by the bootloader code during fastboot (fastboot = 1) and the resulting device frequency. the user is responsible for selecting the bootmode with the appropriate pll multiplier for their mxi/clkin clock source so that the device speed and pll frequency range requirements are met. for the pllc1 clock frequency ranges, see table 6-15 , pllc1 clock frequency ranges in section 6.7.1 , pll1 and pll2. the following are guidelines for pll output frequency and device speed (frequency): pll output frequency: (pllout = clkin frequency * boot pll multiplier) must stay within the pllout frequency range in table 6-15 , pllc1 clock frequency ranges. device frequency: (sysclk1) calculated from table 3-6 and table 3-7 must not exceed the sysclk1 maximum frequency in table 6-15 , pllc1 clock frequency ranges. for example, for a 300-mhz device with a clkin = 27 mhz, in order to stay within the pllout frequency range and sysclk1 maximum frequency from table 6-15 , pllc1 clock frequency ranges, the user must select a boot mode with a pll1 multiplier between x15 and x22. as shown in table 3-5 , table 3-6 , and table 3-7 , there are different types of emifa boot modes. this subsection summarizes these types of emifa boot modes. for further detailed information, see the using the tms320dm643x bootloader application report (literature number spraag0 ). emifa rom direct boot in pll bypass mode (fastboot = 0, bootmode[3:0] = 0100b) ? the c64x+ fetches the code directly from emifa chip select 2 space [ em_cs2] (address 0x4200 0000) ? the pll is in bypass mode ? emifa is configured as asynchronous emif. the user is responsible for ensuring the desirable asynchronous emif pins are available through configuration pins aem[2:0] and aeaw[2:0]. aem[2:0] must be configured to 001b [8-bit emifa (async) pinout mode 1]. emifa rom fastboot with ais (fastboot = 1, bootmode[3:0] = 0100b) ? the c64x+ begins execution from the internal bootloader rom at address 0x0010 0000. ? the bootloader code programs pllc1 to pll mode to speed up the boot process. the pll multiplier value is determined by the aem[2:0] and pllms[2:0] configurations as shown in table 3-6 and table 3-7 . ? the bootloader code reads code from the emifa em_cs2 space using the application image script (ais) format. ? emifa is configured as asynchronous emif. the user is responsible for ensuring the desirable asynchronous emif pins are available through configuration pins aem[2:0] and aeaw[2:0]. aem[2:0] must be configured to 001b [8-bit emifa (async) pinout mode 1]. emifa rom fastboot without ais: (fastboot = 1, bootmode[3:0] = 1001b) ? the c64x+ begins execution from the internal bootloader rom at address 0x0010 0000. ? the bootloader code programs pllc1 to pll mode to speed up the boot process. the pll multiplier value is determined by the aem[2:0] and pllms[2:0] configurations as shown in table 3-6 and table 3-7 . ? the bootloader code then jumps to the emifa em_cs2 space, at which point the c64x+ fetches the code directly from address 0x4200 0000. ? emifa is configured as asynchronous emif. the user is responsible for ensuring the desirable asynchronous emif pins are available through configuration pins aem[2:0] and aeaw[2:0]. aem[2:0] must be configured to 001b [8-bit emifa (async) pinout mode 1]. submit documentation feedback device configurations 69
3.4.1.4 serial boot modes (i2c, uart[uart0], spi[mcbsp0]) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com nand flash boot: (fastboot = 0 or 1, bootmode[3:0] = 0111b) ? the c64x+ begins execution from the internal bootloader rom at address 0x0010 0000. ? depending on the fastboot, aem[2:0], and pllms[2:0] settings, the bootloader code may program the pllc1 to pll mode to speed up the boot process. see table 3-5 , table 3-6 , and table 3-7 . ? the bootloader code reads the code from emifa (nand) em_cs2 (address 0x4200 0000) using ais format. ? emifa is configured in nand mode. the user is responsible for ensuring the desirable asynchronous emif pins are available through configuration pins aem[2:0] and aeaw[2:0]. aem[2:0] can be configured to 001b [8-bit emifa (async) pinout mode 1] or 101b [8-bit emifa (nand) pinout mode 5]. this subsection discusses how the bootloader configures the clock dividers for the serial boot modes?i2c boot, uart boot, and spi boot. 3.4.1.4.1 i2c boot if fastboot = 0, then i2c boot (bootmode = 0101) is performed in standard-mode (up-to 100 kbps). if fastboot = 1, then i2c boot is performed in fast-mode (up-to 400 kbps). the actual i2c data transfer rate is dependent on the mxi/clkin frequency. this is how the bootloader programs the i2c: i2c boot in fast-mode (bootmode[3:0] = 0101b, fastboot = 1) ? i2c register settings: icpsc.ipsc = 2 10 , icclkl.iccl = 8 10 , icckh.icch = 8 10 ? resulting in the following i2c prescaled module clock frequency (internal i2c clock): (clkin frequency in mhz) / 3 ? resulting in the following i2c serial clock (scl): scl frequency (in khz) = (clkin frequency in mhz) / 78 * 1000 scl low pulse duration (in m s) = 39 / (clkin frequency in mhz) scl high pulse duration (in m s) = 39 / (clkin frequency in mhz) i2c boot in standard-mode (bootmode[3:0] = 0101b, fastboot = 0) ? i2c register settings: icpsc.ipsc = 2 10 , icclkl.iccl = 45 10 , icckh.icch = 45 10 ? resulting in the following i2c prescaled module clock frequency (internal i2c clock): (clkin frequency in mhz) / 3 ? resulting in the following i2c serial clock (scl): scl frequency (in khz) = (clkin frequency in mhz) / 300 * 1000 scl low pulse duration (in m s) = 150 / (clkin frequency in mhz) scl high pulse duration (in m s) = 150 / (clkin frequency in mhz) note: the i2c peripheral requires that the prescaled module clock frequency must be between 7 mhz and 12 mhz. therefore, the i2c boot is only available for mxi/clkin frequency between 21 mhz and 30 mhz. for more details on the i2c periperhal configurations and clock requirements, see the tms320dm643x dmp inter-integrated circuit (i2c) peripheral user?s guide (literature number spru991 ). device configurations 70 submit documentation feedback
3.4.2 bootmode registers 3.4.2.1 bootcfg register tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 3.4.1.4.2 uart boot for uart boot (bootmode[3:0] = 1000b or 1110b), the bootloader programs the uart0 peripheral as follows: uart0 divisor is set to 15 10 resulting in this uart0 baud rate in kilobit per second (kbps): ? (clkin frequency in mhz) * 1000 / (15 * 16) the user is responsible for ensuring the resulting baud rate is appropriate for the system. the uart0 divisor (/15) is optimized for clkin frequency between 27 to 29 mhz to stay within 5% of the 115200-bps baud rate. for more details on the uart peripheral configurations and clock generation, see the tms320dm643x dmp universal asynchronous receiver/transmitter (uart) user's guide (literature number spru997 ). 3.4.1.4.3 spi boot both 16-bit address spi boot (bootmode = 0110) and 24-bit address spi boot are performed through the mcbsp0 peripheral. the bootloader programs the mcbsp0 peripheral as follows: mcbsp0 register settings: srgr.clkgdv = 2 10 resulting in this spi serial clock frequency: ? (sysclk3 frequency in mhz) / 3 sysclk3 frequency = sysclk1 frequency / 6. sysclk1 frequency during boot can be found in table 3-5 , table 3-6 , table 3-7 , and/or table 3-8 based on the boot mode selection. for example, if bootmode[3:0] = 0110b, fastboot = 1, the mxi/clkin frequency = 27 mhz, aem[2:0] = 000b, pllms[2:0] = 100b, the combination of table 3-7 and table 3-8 indicates that the device frequency (sysclk1) is clkin x 22 / 2 = 297 mhz. this means sysclk3 frequency is 297 / 6 = 49.5 mhz, resulting in spi serial clock frequency of 49.5 / 3 = 16.5 mhz. the device bootmode (see section 3.4.1 , boot modes) and configuration pins (see section 3.5.1 , device and peripheral configurations at device reset) latched at reset are captured in the device boot configuration (bootcfg) register which is accessible through the system module. this is a read-only register. the bits show the values latched from the corresponding configuration pins sampled at device reset. for more information on how these pins are sampled at device reset, see section 6.5.1.2 , latching boot and configuration pins. for the corresponding device boot and configuration pins, see table 2-5 , boot terminal functions. 31 20 19 18 17 16 reserved fastboot reserved r-0000 0000 0001 r-l r-000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsv pllms rsv daem reserved bootmode r-0 r-lll r-0 r-lll r-0000 r-llll legend: r = read only; l = pin state latched at reset rising edge; - n = value after reset figure 3-3. bootcfg register?0x01c4 0014 submit documentation feedback device configurations 71
3.4.2.2 bootcmplt register tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-9. bootcfg register description bit field name description 31:20 reserved reserved. writes have no effect. fastboot (see section 3.4.1.1 , fastboot) this field is used by the device bootloader code to determine if it needs to speed up the device to pll mode before booting. 19 fastboot 0 = no fastboot 1 = fastboot the default value is latched from fastboot configuration pin. 18:15 rsv reserved. writes have no effect. pinmux0.aeaw default [aeaw] and fastboot pll multiplier select [pllms] (see section 3.5.1.2 , emifa address width select [aeaw] and fast boot pll multiplier select [pllms]) the aeaw[2:0]/pllms configuration pins serve two purposes: aeaw[2:0]: 8-bit emifa (async) pinout mode 1 address width if aem = 001, this field serves as aeaw and it indicates the 8-bit emifa (async) pinout mode 1 address width. in this case, this field affects pin mux control only by setting the default of pin mux control register 14:12 pllms pinmux0.aeaw[2:0]. this field does not affect emifa register settings. for more details on the aeaw settings, see section 3.7.2.1 , pinmux0 register description. pllms: fastboot pll multiplier select if fastboot = 1 and aem[2:0] = 000b or 101b, this field selects the fastboot pll multiplier. in this case, this field does not affect the pin mux control or the emifa register settings. the bootloader code uses this field to determine the pll multiplier used for fastboot. 11 rsv reserved. writes have no effect. pinmux0.aem default [daem] (see section 3.5.1.1 , emifa pinout mode (aem[2:0])) for more details on the aem settings, see section 3.7.2.1 , pinmux0 register description. 10:8 daem this field affects pin mux control by setting the default of pinmux0.aem. this field does not affect emifa register settings. the default value is latched from the aem[2:0] configuration pins. 7:4 reserved reserved. writes have no effect. boot mode (see section 3.4.1 , boot modes) 3:0 bootmode this field is used in conjunction with fastboot, aem, and pllms to determine the device boot mode. the default value is latched from the bootmode[3:0] configuration pins. if the bootloader code detects an error during boot, it records the error status in the boot complete (bootcmplt) register. the bootcmplt register is reset by any device-level global reset. for the list of device-level global resets, see section 6.5 , reset. device configurations 72 submit documentation feedback
3.4.2.3 dspbootaddr register tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 31 20 19 16 reserved err r/w-0000 0000 0000 r/w-0000 15 0 reserved r/w-0000 0000 0000 0000 legend: r = read; w = write; - n = value after reset figure 3-4. bootcmplt register? 0x01c4 000c table 3-10. bootcmplt register description bit field name description 31:20 reserved reserved. for proper device operation, the user should only write "0" to these bits. boot error 0000 = no error (default). 19:16 err 0001 - 1111 = bootloader software detected a boot error and aborted the boot. for the error codes, see the using the tms320dm643x bootloader application report (literature number spraag0 ). 15:0 reserved reserved. for proper device operation, the user should only write "0" to these bits. the dsp boot address (dspbootaddr) register contains the starting address for the c64x+ cpu. whenever the c64x+ is released from reset, it begins executing from the location pointed to by dspbootaddr register. software can leave the dspbootaddr register at default. the dspbootaddr register is reset by any device-level global reset. for the list of device-level global resets, see section 6.5 , reset. 31 0 dspbootaddr r/w-0x0010 0000 or 0x4200 00000 legend: r = read; w = write; - n = value after reset figure 3-5. dspbootaddr register? 0x01c4 0008 table 3-11. dspbootaddr register description bit field name description dsp boot address after boot, the c64x+ cpu begins execution from this 32-bit address location. the lower 10 bits (bits 9:0) should always be programmed to "0" as they are ignored by the c64x+. the default value of the dspbootaddr depends on the boot mode selected. 31:0 dspbootaddr the dspbootaddr defaults to 0x0010 0000 when the internal bootloader rom is used. or the dspbootaddr defaults to 0x4200 0000 when emifa cs2 space is used. for the boot mode selections, see table 3-5 , non-fastboot modes; table 3-6 , fixed-multiplier fastboot modes; and table 3-7 , user-select multiplier fastboot modes. submit documentation feedback device configurations 73
3.5 configurations at reset 3.5.1 device and peripheral configurations at device reset tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com some device configurations are determined at reset. the following subsections give more details. table 2-5 , boot terminal functions lists the device boot and configuration pins that are latched at device reset for configuring basic device settings for proper device operation. table 3-12 , summarizes the device boot and configuration pins, and the device functions that they affect. table 3-12. default functions affected by device boot and configuration pins device boot and configuration boot selected pin mux control global setting peripheral setting pins (1) bootmode[3:0] boot mode pinmux0/pinmux1 i/o pin power: psc/peripherals: registers: based on based on based on bootmode[3:0], the bootmode[3:0], the bootmode[3:0], the bootloader code programs bootloader code programs bootloader code programs vdd3p3v_pwdn register the psc to put pinmux0 and pinmux1 to power up the i/o pins boot-related peripheral(s) registers to select the required for boot. in the enable state, and appropriate pin functions programs the peripheral(s) required for boot. for boot operation. fastboot fastboot ? sets device frequency: ? based on bootmode, fastboot, pllms, and aem the bootloader code programs pllc1. aeaw[2:0]/pllms[2:0] if fastboot = 1 and pinmux0.aeaw: sets device frequency: ? aem = 000b or 101b the aeaw[2:0] sets the based on bootmode, pllms[2:0] selects the default of this field to fastboot, pllms, and fastboot pll control the emifa aem the bootloader code multiplier. address bus width ( only programs pllc1. applicable if pinmux0.aem = 001b). affects the pin muxing in emifa/vpss sub-block 0. aem[2:0] together with fastboot pinmux0.aem: sets device frequency: psc/emifa: and pllms[2:0] , sets the default of this based on bootmode, the emifa module state determines the field to control the emifa fastboot, pllms, and defaults to swrstdisable fastboot pll pinout mode. aem the bootloader code if aem = 0; otherwise, the multiplier. programs pllc1. emifa module state affects the pin muxing in defaults to enable. emifa/vpss sub-block 0, 1, and 3. (1) software can modify all pinmux0 and pinmux1 bit fields from their defaults. for proper device operation, external pullup/pulldown resistors may be required on these device boot and configuration pins. for discussion situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. note: all dm6431 configuration inputs (bootmode[3:0], fastboot, aeaw[2:0]/pllms[2:0] and aem[2:0]) are multiplexed with other functional pins. these pins function as device boot and configuration pins only during device reset. the user must take care of any potential data contention in the system. to help avoid system data contention, the dm6431 puts these configuration pins into a high-impedance state (hi-z) when device reset ( reset or por) is asserted, and continues to hold them in a high-impedance state until the internal global reset is removed; at which point, the default peripheral (either gpio or emifa based on default of aem[2:0]) will now control these pins. all of the device boot and configuration pin settings are captured in the corresponding bit fields in the bootcfg register (see section 3.4.2.1 ). device configurations 74 submit documentation feedback
3.5.1.1 emifa pinout mode (aem[2:0]) 3.5.1.2 emifa address width select (aeaw) and fastboot pll multiplier select (pllms) 3.6 configurations after reset tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the following subsections provide more details on the device configurations determined at device reset: aem and aeaw/pllms. to support different usage scenarios, the dm6431 provides intricate pin multiplexing between the emifa and other peripherals. the pinmux0.aem register bit field in the system module determines the emifa pinout mode. the aem[2:0] pins only select the default emifa pinout mode. it is latched at device reset de-assertion (high) into the bootcfg.daem bit field. the aem[2:0] value also sets the default of the pinmux0.aem bit field. while the bootcfg.daem bit field shows the actual latched value and cannot be modified, the pinmux0.aem value can be changed by software to modify the emifa pinout mode. note: the aem[2:0] value does not affect the operation of the emifa module itself. it only affects which emifa pins are brought out to the device pins. for more details on the aem settings, see section 3.7 , multiplexed pin configurations. in addition, for fastboot modes (fastboot = 1), the bootloader code determines the pll1 multiplier based on the default settings of aem[2:0] and pllms[2:0]. for more details, see section 3.4.1.1 , fastboot, and section 3.5.1.2 , emifa address width select (aeaw) and fastboot pll multiplier select (pllms). the aeaw[2:0]/pllms[2:0] pins serve two functional purposes (aeaw or pllms), depending on the fastboot and aem settings. the aeaw[2:0]/pllms[2:0] pins are latched at device reset de-assertion (high) and captured in the bootcfg.pllms bit field. this value also sets the default of the pinmux0.aeaw field. while the bootcfg.pllms field shows the actual latched value and cannot be modified, the pinmux0.aeaw value can be changed by software to modify the emifa pinout. aeaw as emifa address width select (aeaw) if aem[2:0] = 001b [8-bit emifa (async) pinout mode 1], the aeaw[2:0]/pllms[2:0] pins serve as aeaw to set the default of the emifa address width selection. when emifa is used in the 8-bit emifa (async) pinout mode 1 (pinmux0.aem = 001b), the user has the option to determine how many address pins are needed. the unused address pins can be used as general-purpose input/output (gpio) pins or extra data pins for vpfe. for more details on how the aeaw settings control the exact pin out when aem = 001b, see section 3.7.3.11 , emifa/vpss block muxing. for other emifa pinout modes (aem not 001b), aeaw is not applicable in determining the emifa address width. note: aeaw[2:0] value does not affect the operation of the emifa module itself. it only affects which of the emifa address bits are brought out to the device pins. aeaw as fast boot pll multiplier select (pllms) if fastboot = 1, and aem[2:0] = 000b [no emifa] or 101b [8-bit emifa (nand) pinout mode 5], the aeaw[2:0]/pllms[2:0] pins serve as pllms to select pll multiplier for fastboot modes. for more information on boot modes and the fastboot pll multiplier selection, see section 3.4.1 , boot modes. the following sections provide details on configuring the device after reset. multiplexed pins are configured both at and after reset. section 3.5.1 , device and peripheral configurations at device reset, discusses multiplexed pin control at reset. for more details on multiplexed pins control after reset, see section 3.7 , multiplexed pin configurations. submit documentation feedback device configurations 75
3.6.1 switch central resource (scr) bus priorities tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com prioritization within the switched central resource (scr) is programmable for each master. the register bit fields and default priority levels for dm6431 bus masters are shown in table 3-13 , dm6431 default bus master priorities. the priority levels should be tuned to obtain the best system performance for a particular application. lower values indicate higher priority. for most masters, their priority values are programmed at the system level by configuring the mstpri0 and mstpri1 registers. details on the mstpri0/1 registers are shown in figure 3-6 and figure 3-7 . the c64x+, vpss, and edma masters contain registers that control their own priority values. table 3-13. dm6431 default bus master priorities priority bit field bus master default priority level vpssp vpss 0 (vpss pcr register) edmatc0p edmatc0 0 (edmacc quepri register) edmatc1p edmatc1 0 (edmacc quepri register) edmatc2p edmatc2 0 (edmacc quepri register) c64x+_dmap c64x+ (dma) 7 (c64x + mdmaarbe.pri field) c64x+_cfgp c64x+ (cfg) 1 (mstpri0 register) emacp emac 4 (mstpri1 register) 31 16 reserved r-0000 0000 0000 0000 15 11 10 8 7 0 reserved c64x+_cfgp reserved r-0000 0 r/w-001 r-0000 0000 legend: r = read; w = write; - n = value after reset figure 3-6. mstpri0 register? 0x01c4 003c table 3-14. mstpri0 register description bit field name description 31:11 reserved reserved. read-only, writes have no effect. c64x+_cfg master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 10:8 c64x+_cfgp 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 7:0 reserved reserved. read-only, writes have no effect. 76 device configurations submit documentation feedback
3.6.2 peripheral selection after device reset 3.6.2.1 timer control register (timerctl) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 31 27 26 25 24 23 22 21 20 19 18 17 16 reserved rsv rsv rsv rsv rsv r-0000 0 r/w-100 r-0 r/w-100 r-0 r/w-100 15 3 2 1 0 reserved emacp r- 0000 0000 0000 0 r/w-100 legend: r = read; w = write; - n = value after reset figure 3-7. mstpri1 register? 0x01c4 0040 table 3-15. mstpri1 register description bit field name description 31:27 reserved reserved. read-only, writes have no effect. reserved. for proper device operation, the user must only write "100" to 26:24 rsv these bits. 23 rsv reserved. read-only, writes have no effect. reserved. for proper device operation, the user must only write "100" to 22:20 rsv these bits. 19 rsv reserved. read-only, writes have no effect. reserved. for proper device operation, the user must only write "100" to 18:16 rsv these bits. 15:3 reserved reserved. read-only, writes have no effect. emac master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 2:0 emacp 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) after device reset, most peripheral configurations are done within the peripheral?s registers. this section discusses some additional peripheral controls in the system module. for information on multiplexed pin controls that determine what peripheral pins are brought out to the pins, see section 3.7 , multiplexed pin configurations. the timer control register (timerctl) provides additional control for timer0 and timer2. the user should only modify this register once during device initialization, when the corresponding timer is not in use. timer 2 control: the timerctl.wdrst bit determines if the watchdog timer event (timer 2) can cause a device max reset. for more details on the description of a maximum reset, see section 6.5.3 , maximum reset. timer 0 control: the tinp0sel bit selects the clock source connected to timer0's tin0 input. submit documentation feedback device configurations 77
3.6.2.2 edma tc configuration register (edmatccfg) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com 31 16 reserved r-0000 0000 0000 0000 15 2 1 0 tinp0 wd reserved sel rst r- 0000 0000 0000 00 r/w-0 r/w-1 legend: r = read; w = write; - n = value after reset figure 3-8. timerctl register? 0x01c4 0084 table 3-16. timerctl register description bit field name description 31:2 reserved reserved. read-only, writes have no effect. timer0 external input (tin0) select 0 = timer0 external input comes directly from the tinp0l pin ( default). 1 tinp0sel 1 = timer0 external input is tinp0l pin divided by 6. for example, if tinp0l = 27mhz, timer0 input tin0 is 27mhz / 6 = 4.5 mhz. watchdog reset enable 0 wdrst 0 = watchdog timer event (wdint from timer2) does not cause device reset. 1 = watchdog timer event (wdint from timer2) causes a device max reset ( default). the edma transfer controller configuration (edmatccfg) register configures the default burst size (dbs) for edma tc0, edma tc1, and edma tc2. for more information on the correct usage of dbs, see the tms320dm643x dmp enhanced direct memory access (edma) controller user's guide (literature number spru987 ). the user should only modify this register once during device initialization and when the corresponding edma tc is not in use. 31 16 reserved r-0000 0000 0000 0000 15 6 5 4 3 2 1 0 reserved tc2dbs tc1dbs tc0dbs r-0000 0000 00 r/w-10 r/w-01 r/w-00 legend: r = read; w = write; - n = value after reset figure 3-9. edmatccfg register? 0x01c4 0088 table 3-17. edmatccfg register description bit field description 31:6 reserved reserved. read-only, writes have no effect. edma tc2 default burst size 00 = 16 byte 01 = 32 byte 10 = 64 byte ( default) 5:4 tc2dbs 11= reserved edma tc2 is intended for miscellaneous transfers. tc2 fifo size is 128 bytes, regardless of default burst size setting. device configurations 78 submit documentation feedback
3.7 multiplexed pin configurations tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-17. edmatccfg register description (continued) bit field description edma tc1 default burst size 00 = 16 byte 01 = 32 byte ( default) 10 = 64 byte 3:2 tc1dbs 11 = reserved edma tc1 is intended for high throughput bulk transfers. tc1 fifo size is 256 bytes, regardless of default burst size setting. edma tc0 default burst size 00 = 16 byte ( default) 01 = 32 byte 10 = 64 byte 1:0 tc0dbs 11 = reserved edma tc0 is intended for short burst transfers with stringent deadlines (e.g., mcbsp, mcasp). tc0 fifo size is 128 bytes, regardless of default burst size setting. dm6431 makes extensive use of pin multiplexing to accommodate a large number of peripheral functions in the smallest possible package, providing ultimate flexibility for end applications. the pin multiplex registers pinmux0 and pinmux1 in the system module are responsible for controlling all pin multiplexing functions on the dm6431. the default setting of some of the pinmux0 and pinmux1 bit fields are configured by configuration pins latched at reset (see section 3.5.1 , device and peripheral configurations at device reset). after reset, software may program the pinmux0 and pinmux1 registers to switch pin functionalities. the following peripherals have multiplexed pins: vpss (vpfe), emifa, emac, mcasp0, mcbsp0, pwm0, pwm1, pwm2, timer0, timer1, uart0, hecc, and gpio. the device is divided into the following pin multiplexed blocks (pin mux blocks): emifa/vpss block: vpss (vpfe), emifa, and gpio. this block is further subdivided into these sub-blocks: ? sub-block 0: vpfe (ccdc), part of emifa (address and control), and gpio ? sub-block 1: part of emifa (data, address, control), and gpio ? sub-block 2: part of emifa (control signals em_wait/(rdy/ bsy), em_oe, and em_we) ? sub-block 3: part of emifa (address em_a[12:5]), and gpio host block: emac and gpio serial port block: mcbsp0, mcasp0, and gpio. this block is further sub-divided into sub-blocks. ? serial port sub-block 0: mcbsp0, part of mcasp0, and gpio ? serial port sub-block 1: part of mcasp0 and gpio uart0 flow control block: uart0 flow control, pwm0, and gpio uart0 data block: uart0 data and gpio timer0 block: timer0 and mcbsp0 clks pins timer1 block: timer1 and hecc pwm1 block: pwm1 and gpio clkout block: clkout0, pwm2, and gpio as shown in the list above, the mcbsp0 and uart0 peripherals span multiple pin mux blocks. to use these peripherals, they must be selected in all relevant pin mux blocks. for more details, see section 3.7.3 , pin multiplexing details, and section 3.7.3.2 , peripherals spanning multiple pin mux blocks. note: there is no actual pin multiplexing in emifa/vpss sub-block 2. however, this is still considered a "pin mux block" because it contains part of the pins necessary for emifa. submit documentation feedback device configurations 79
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com a high level view of the pin mux blocks is shown in figure 3-10 . in each pin mux block, the pinmux0/pinmux1 default settings are underlined. note: some default pin functions are determined by configuration pins (aeaw[2:0] and aem[2:0]); therefore, more than one configuration setting can serve as default based on the configuration pin settings latched at device reset. a. default settings for pinmux0 and pinmux1 registers are underlined. b. emifa/vpss block: shows the major config options based on the aem settings. actual pin functions in the emifa/vpss block are further determined by other pinmux fields. c. mcbsp0 pins span multiple blocks (serial port sub-block0 and timer0 block). serial port sub-block0 contains most of the pins needed for mcbsp0 operation. timer0 block contains the optional external clock source input clks0. figure 3-10. pin mux block selection device configurations 80 submit documentation feedback host block (27 pins) (a) gpio (27) hostbk=000 hostbk=100 emac (15) mdio (2) gpio (10) uart0 data block (2 pins) gpio (2) ur0dbk=0 uart data (2) ur0dbk=1 uart0 flow control block (2 pins) gpio (2) ur0fcbk=00 uart0 flowctrl (2) ur0fcbk=01 pwm0 (1) ur0fcbk=10 gpio (1) timer1 block (2 pins) gpio (2) tim1bk=00 timer1 (2) tim1bk=01 hecc (2) tim1bk=11 timer0 block (2 pins) (c) gpio (2) tim0bk=00 timer0 (2) tim0bk=01 mcbsp0 clks0 (1) tim0bk=11 timer0 tinpol (1) pwm 1 block (1 pin) gpio (1) pwm1bk=0 pwm1 (1) pwm1bk=1 clkout block (1 pin) gpio (1) ckobk=00 clkout (1) ckobk=01 pwm2 (1) ckobk=10 serial port sub-block 0 (6 pins) (c) gpio (6) spbk0=00 mcbsp0 (6) spbk0=01 mcasp0 receive and 3 serializers (6) spbk0=10 serial port sub-block 1 (6 pins) gpio (6) spbk1=00 mcasp0 transmit and 1 serializer (6) spbk1=10 emifa/vpss block (61 pins) (a)(b) major config option a 8-10b vpfe gpio major configoption b gpio 8-10b vpfe 8b emifa (async) pinout mode 1 32kb-16mb per ce major configoption e gpio 8-10b vpfe 8b emifa (nand) pinout mode 5 aem=000 aem=001 aem=101
3.7.1 pin muxing selection at reset 3.7.2 pin muxing selection after reset 3.7.2.1 pinmux0 register description tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 this section summarizes pin mux selection at reset. the configuration pins aem[2:0] and aeaw[2:0] latched at device reset determine default pin muxing for the following pin mux blocks: emifa/vpss block: default pin mux determined by aem[2:0] and aeaw[2:0]. after reset, software may modify settings in the pinmux0 register to add vpfe functionalities into this block. ? aem[2:0] = 000b, aeaw[2:0] = don't care: major config option a is selected. this block defaults to 61 gpio pins. ? aem[2:0] = 001b, aeaw[2:0] = 000b to 100b: major config option b is selected. this block defaults to 8-bit emifa (async) pinout mode 1, plus 24-to-32 gpio pins. ? aem[2:0] = 101b, aeaw[2:0] = don't care: major config option e is selected. this block defaults to 8-bit emifa (nand) pinout mode 5, plus 47 gpio pins. for a description of the pinmux0 and pinmux1 registers and more details on pin muxing, see section 3.7.2 , pin muxing selection after reset. the pinmux0 and pinmux1 registers in the system module allow software to select the pin functions in the pin mux blocks. the pin control of some of the pin mux blocks requires a combination of pinmux0/pinmux1 bit fields. for more details on the combination of the pinmux bit fields that control each muxed pin, see section 3.7.3.1 , multiplexed pins on dm6431. this section only provides an overview of the pinmux0 and pinmux1 registers. for more detailed discussion on how to program each pin mux block, see section 3.7.3 , pin multiplexing details. the pin multiplexing 0 register (pinmux0) controls the pin function in the emifa/vpss block. the pinmux0 register format is shown in figure 3-11 and the bit field descriptions are given in table 3-18 . some muxed pins are controlled by more than one pinmux bit field. for the combination of the pinmux bit fields that control each muxed pin, see section 3.7.3.1 , multiplexed pins on dm6431. for more information on emifa/vpss block pin muxing, see section 3.7.3.11 , emifa/vpss block muxing. for the pin-by-pin muxing control of the emifa/vpss block, see section 3.7.3.11.7 , emifa/vpss block pin-by-pin multiplexing summary. 31 30 29 25 24 23 22 21 20 19 18 17 16 cfldse cwen ccdcse rsv ci10sel reserved hvdsel rsv rsv aeaw l sel l r/w-0 r/w-0 r/w-00 000 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-lll 15 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cs3sel cs4sel cs5sel reserved aem r/w-0000 r/w-00 r/w-00 r/w-00 r/w-000 r/w-lll legend: r/w = read/write; r = read only; l = pin state latched at reset rising edge; - n = value after reset (1) for proper dm6431 device operation, always write a value of "0" to all reserved/rsv bits. figure 3-11. pinmux0 register? 0x01c4 0000 (1) submit documentation feedback device configurations 81
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-18. pinmux0 register description bit field name description pins controlled reserved. for proper device operation, the user should only write "0" to this bit 31 rsv ( default). sub-block 0 ci[1:0] function select. ci1(ccd9)/em_a[19]/gp[45] 0 = no ccdc ci[1:0]. ci0(ccd8)/em_a[20]/gp[44] 30 ci10sel pins function as gpio or emifa based on aem and aeaw settings ( default). the combination of pinmux0 fields aem, 1 = selects ccdc [1:0] (as ccd8 and ccd9, respectively) to get a 10-bit ccdc. aeaw, and ci10sel bits control the pin to use the 10-bit ccdc, the user must also configure pinmux0.ccdcsel = 1. muxing of these 2 pins. (1) reserved. for proper device operation, the user should only write "0" to this bit 29:25 rsv ( default). sub-block 0 ccdc field select. c_field/em_a[21]/gp[34] 0 = no ccdc field (c_field). 24 cfldsel pin functions as emifa em_a[21] or gpio based on aem setting ( default). the combination of pinmux0/1 fields cfldsel and aem control the muxing of this 1 = ccdc field (c_field). pin. (1) ccdc write enable select. sub-block 0 0 = no ccdc write enable. pin functions as emifa em_r/ w or gpio based on aem setting ( default). c_we/em_r/ w/gp[35] 23 cwensel 1 = ccdc write enable (c_we). the combination of pinmux0 fields cwensel pin functions as ccdc write enable c_we. and aem control the muxing of this pin. (1) applicable only for aem = 0 (000b) or 5 (101b). sub-block 0 ccdc hd and vd select. vd/gp[53] 0 = no ccdc hd and vd. 22 hvdsel hd/gp[52] pins function as gpio (gp[53] and gp[52]) ( default). the pinmux0 field hvdsel alone controls the 1 = ccdc hd and vd. muxing of these 2 pins. reserved. for proper device operation, the user should only write "0" to this bit 21 rsv ( default). sub-block 0 pclk/gp[54] yi7(ccd7)/gp[43] ccdc select. yi6(ccd6)/gp[42] this bit field determines if ccdc is supported or not. yi5(ccd5)/gp[41] 0 = ccdc not supported. yi4(ccd4)/gp[40] 20 ccdcsel pins function as gpio (gp[54] and gp[43:36]) ( default). yi3(ccd3)/gp[39] yi2(ccd2)/gp[38] 1 = ccdc supported. yi1(ccd1)/gp[37] pins function as ccdc pclk, yi[7:0]. yi0(ccd0)/gp[36] the pinmux0 field ccdcsel alone controls the muxing of these 9 pins. reserved. for proper device operation, the user should only write "0" to this bit 19 rsv ( default). (1) for the full set of valid configurations of these pins, see section 3.7.3.11.7 , emifa/vpss block pin-by-pin multiplexing summary. 82 device configurations submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-18. pinmux0 register description (continued) bit field name description pins controlled 8-bit emifa (async) pinout mode 1 address width select or fast boot pll multiplier select this field serves two purposes: 1. if aem = 001b, this field serves as the 8-bit emifa (async) pinout mode 1 address width select. 2. if fastboot = 1 and aem = 0 (000b) or 5 (101b), this field serves as the fastboot pll multiplier select. fastboot pll multiplier select: for more details on the aeaw pin functions as fastboot pll multiplier select, see section 3.4.1 , bootmodes. emifa address width select: sub-block 0 000b = emifa (async) pinout supports only em_a[12:0] address pins. emifa (async) signals em_a[20:13] are not pinned out. you get 6 gpio pins em_a[13]/gp[51] gp[51:46] and pinmux bit field ci10sel determines the function of the other em_a[14]/gp[50] 2 pins. em_a[15]/gp[49] em_a[16]/gp[48] 001b = emifa (async) pinout supports only em_a[14:0] address pins. em_a[17]/gp[47] emifa (async) signals em_a[14:13] are pinned out. 18:16 aeaw (1) em_a[18]/gp[46] emifa (async) signals em_a[20:15] are not pinned out. you get 4 gpio pins ci1(ccd9)/em_a[19]/gp[45] gp[49:46] and pinmux0 bit field ci10sel determines the function of the other ci0(ccd8)/em_a[20]/gp[44] 2 pins. the combination of pinmux0 fields aem, 010b = emifa (async) pinout supports only address pins em_a[16:0]. aeaw, and ci10sel control the muxing of emifa (async) signals em_a[16:13] are pinned out. these 8 pins. (2) emifa (async) signals em_a[20:17] are not pinned out. you get 2 gpio pins gp[47:46] and pinmux0 bit field ci10sel determines the function of the other 2 pins. 011b = emifa (async) pinout supports only address pins em_a[18:0]. emifa (async) signals em_a[18:13] are pinned out. emifa (async) signals em_a[20:19] are not pinned out. pinmux0 bit field ci10sel determines the function of these 2 pins. 100b = emifa (async) pinout supports address pins em_a[20:0]. emifa (async) signals em_a[20:13] are pinned out. pinmux0 bit field ci10sel must be programmed to 0. 101b through 111b = reserved. reserved. for proper device operation, the user should only write "0" to these bits 15:12 reserved ( default). chip select 3 select. sub-block 1 00 = gpio pin (gp13) ( default) em_cs3/gp[13] 11:10 cs3sel 01 = emifa chip select 3 ( em_cs3) the pinmux0 field cs3sel alone controls the 10 = reserved muxing of this pin. 11 = reserved chip select 4 select. sub-block 1 00 = gpio pin (gp32) ( default) em_cs4/gp[32] 9:8 cs4sel 01 = emifa chip select 4 ( em_cs4) the pinmux0 field cs4sel alone controls the 10 = reserved muxing of this pin. 11 = reserved chip select 5 select. sub-block 1 00 = gpio pin (gp33) ( default) em_cs5/gp[33] 7:6 cs5sel 01 = emifa chip select 5 ( em_cs5) the pinmux0 field cs5sel alone controls the 10 = reserved muxing of this pin. 11 = reserved reserved. for proper device operation, the user should only write "0" to these bits 5:3 reserved ( default). (1) the aeaw default value is latched at reset from aeaw[2:0] configuration inputs. the latched values are also shown at bootcfg.pllms ( read-only). (2) for the full set of valid configurations of these pins, see section 3.7.3.11.7 , emifa/vpss block pin-by-pin multiplexing summary. submit documentation feedback device configurations 83
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-18. pinmux0 register description (continued) bit field name description pins controlled sub-block 0 c_we/em_r/ w/gp[35] c_field/em_a[21]/gp[34] em_a[13]/gp[51] em_a[14]/gp[50] em_a[15]/gp[49] em_a[16]/gp[48] em_a[17]/gp[47] em_a[18]/gp[46] ci1(ccd9)/em_a[19]/gp[45] ci0(ccd8)/em_a[20]/gp[44] emifa pinout modes sub-block 1 this field does not affect the actual emifa operation. it only determines what multiplexed pins in the emifa/vpss block serves as emifa pins. em_d[7]/gp[21] em_d[6]/gp[20] 000b = no emifa mode. em_d[5]/gp[19] none of the multiplexed pins in the emifa/vpss block serves as emifa pins. em_d[4]/gp[18] em_d[3]/gp[17] 001b = 8-bit emifa (async) pinout mode 1. em_d[2]/gp[16] (up to 16m-byte address reach per chip select space). em_d[1]/gp[15] pinout allows up to a maximum of these functions from emifa/vpss block: 8-bit em_d[0]/gp[14] emifa (async or nand) + 10-bit ccdc (vpfe) 2:0 aem (1) em_cs2/gp[12] em_a[3]/gp[11] 010b = reserved. em_a[4]/gp[10]/(aeaw2/pllms2) 011b = reserved. em_a[1]/(ale)/gp[9]/(aeaw1/pllms1) em_a[2]/(cle)/gp[8]/(aeaw0/pllms0) 100b = reserved. em_a[0]/gp[7]/(aem2) em_ba[0]/gp[6]/(aem1) 101b = 8-bit emifa (nand) pinout mode 5. em_ba[1]/gp[5]/(aem0) pinout allows up to a maximum of these functions from emifa/vpss block: 8-bit emifa (nand) + 10-bit ccdc (vpfe) sub-block3 110b through 111b = reserved. em_a[12]/gp[89] em_a[11]/gp[90] em_a[10]/gp[91] em_a[9]/gp[92] em_a[8]/gp[93] em_a[7]/gp[94] em_a[6]/gp[95] em_a[5]/gp[96] the pin mux for these pins are controlled by a combination of aem and other pinmux0 fields, including cwensel, cfldsel, aeaw, and ci10sel. (2) (1) the aem default value is latched at reset from aem[2:0] configuration inputs. the latched values are also shown at bootcfg.daem ( read-only). (2) for the full set of valid configurations of these pins, see section 3.7.3.11.7 , emifa/vpss block pin-by-pin multiplexing summary. 84 device configurations submit documentation feedback
3.7.2.2 pinmux1 register description tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the pin multiplexing 1 register (pinmux1) controls the pin multiplexing of all pin mux blocks except the emifa/vpss block. the pinmux1 register format is shown in figure 3-12 and the bit field descriptions are given in table 3-19 . some muxed pins are controlled by more than one pinmux bit field. for the combination of pinmux bit fields that control each muxed pin, see section 3.7.3.1 , multiplexed pins on dm6431. 31 26 25 24 23 22 21 20 19 18 17 16 reserved spbk1 spbk0 tim1bk rsv tim0bk r/w-0000 00 r/w-00 r/w-00 r/w-00 r/w-00 r/w-00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwm1b ckobk rsv ur0fcbk rsv ur0dbk rsv hostbk reserved rsv k r/w-01 r/w-0 r/w-0 r/w-00 r/w-0 r/w-0 r/w-0 r/w-000 r/w-000 r-0 legend: r/w = read/write; r = read only; p = specified pin state; - n = value after reset (1) for proper dm6431 device operation, always write a value of "0" to all reserved/rsv bits. figure 3-12. pinmux1 register? 0x01c4 0004 (1) table 3-19. pinmux1 register description bit field name description pins controlled reserved. for proper device operation, the user should only write "0" to this bit 31:26 reserved ? ( default). serial port sub-block 1 pin select. selects the function of the multiplexed pins in the serial port sub-block 1. serial port sub-block 1: 00 = gpio mode ( default). axr0[0]/gp[105] pins function as gpio (gp[110:105]). aclkx0/gp[106] 25:24 spbk1 01 = reserved. afsx0/gp[107] ahclkx0/gp[108] 10 = mcasp0 transmit and 1 serializer. amutein0/gp[109] pins function as mcasp0: axr0[0], aclkx0, afsx0, ahclkx0, amutein0, amute0/gp[110] and amute0. 11 = reserved. serial port sub-block 0 pin select. selects the function of the multiplexed pins in the serial port sub-block 0. 00 = gpio mode ( default). serial port sub-block 0: pins function as gpio (gp[104:99]). aclkr0/clkx0/gp[99] afsr0/dr0/gp[100] 01 = mcbsp0 mode. 23:22 spbk0 ahclkr0/clkr0/gp[101] pins function as mcbsp0 clkx0, fsx0, dx0, clkr0, fsr0, and dr0. axr0[3]/fsr0/gp[102] axr0[2]/fsx0/gp[103] 10 = mcasp0 receive and 3 serializers. axr0[1]/dx0/gp[104] pins function as mcasp0 aclkr0, afsr0, ahclkr0, axr0_3, axr0_2, and axr0_1. 11 = reserved timer1 block pin select. selects the function of the multiplexed pins in thetimer1 block. 00 = gpio mode ( default). pins function as gpio (gp[56:55]). timer1 block: 21:20 tim1bk 01 = timer1 mode. hecc_rx/tinp1l/gp[56] pins function as timer1 tinp1l and tout1l. hecc_tx/tout1l/gp[55] 10 = reserved 11 = hecc mode. pins function as hecc hecc_rx and hecc_tx. reserved. for proper device operation, the user should only write "0" to this bit 19:18 rsv ? ( default). submit documentation feedback device configurations 85
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-19. pinmux1 register description (continued) bit field name description pins controlled timer0 block pin select. selects the function of the multiplexed pins in the timer0 block. 00 = gpio mode ( default). pins function as gpio (gp[98:97]). timer0 block: 01 = timer0 mode. 17:16 tim0bk tinp0l/gp[98] pins function as timer0 tinp0l and tout0l. clks0/tout0l/gp[97] 10 =reserved. 11 = mcbsp0 external clock source + timer0 input mode. pins function as mcbsp0 external clock source clks0, and timer0 input tinp0l. clkout block pin select. selects the function of the multiplexed pins in the clkout block. 00 = gpio mode. pin functions as gpio (gp[84]). clkout block: 15:14 ckobk 01 = clkout mode ( default). clkout0/pwm2/gp[84] pin functions as device clock output clkout0, sourced from pllc1 obsclk. 10 = pwm2 mode. pin functions as pwm2. 11 = reserved reserved. for proper device operation, the user should only write "0" to this bit 13 rsv ? ( default). pwm1 block pin select. selects the function of the multiplexed pins in the pwm1 block. 0 = gpio mode ( default). pwm1 block: 12 pwm1bk pin functions as gpio (gp[4]). gp[4]/pwm1 1 = pwm1 mode. pin functions as pwm1. uart0 flow control block pin select. selects the function of the multiplexed pins in the uart0 flow control block. 00 = gpio mode ( default). pins function as gpio (gp[88:87]). uart0 flow control block: 11:10 ur0fcbk 01 = uart0 flow control mode. ucts0/gp[87] pins function as uart0 flow control ucts0 and urts0. urts0/pwm0/gp[88] 10 = pwm0 + gpio mode. pins function as pwm0 and gpio (gp[87]). 11 = reserved reserved. for proper device operation, the user should only write "0" to this bit 9 rsv ? ( default). uart0 data block pin select. selects the function of the multiplexed pins in the uart0 data block. uart0 data block: 0 = gpio mode ( default). 8 ur0dbk urxd0/gp[85] pins function as gpio (gp[86:85]). utxd0/gp[86] 1 = uart0 data mode. pins function as uart0 data urxd0 and utxd0. 86 device configurations submit documentation feedback
3.7.3 pin multiplexing details 3.7.3.1 multiplexed pins on dm6431 tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-19. pinmux1 register description (continued) bit field name description pins controlled reserved. for proper device operation, the user should only write "0" to this bit 7 rsv ? ( default). host block: gp[57] gp[58] gp[59] gp[60] gp[61] host block pin select. gp[62] if emac opertaion is desired, emac must be placed in reset before gp[63] programminng pinmux1 hostbk to select emac pins. gp[64] gp[65] hostbk = 000: gpio mode ( default). gp[66] pins function as gpio (gp[83:57]). mcol/ gp[67] mcrs/ gp[68] hostbk = 001: reserved mtxd3/ gp[69] 6:4 hostbk hostbk = 010: reserved mtxd2/gp[70] mtxd1/gp[71] hostbk = 011: reserved mtxd0/gp[72] mtxclk/gp[73] hostbk = 100: mii + mdio +10 gpio mode. mrxdv/gp[74] pins function as mii (txclk, crs, col, txd[3:0], rxvd, txen, rxer, mtxen/gp[75] rxclk, rxd[3:0]), mdio (mdio, mdc), and gp[66:57]. mrxer/gp[76] mrxclk/gp[77] all other hostbk combinations reserved. mrxd0/gp[78] mrxd1/gp[79] mrxd2/ gp[80] mdclk/gp[81] mrxd3/gp[82] mdio/gp[83] reserved. for proper device operation, the user should only write "0" to this bit 3:1 reserved ? ( default). 0 rsv reserved. writes have no effect. ? this section discusses how to program each pin mux block to select the desired peripheral functions. the following steps can be used to determine pin muxing suitable for the application: 1. understand the major configuration choices available for the specific application. a. device major configuration choices: figure 3-10 shown in section 3.7 , multiplexed pin configurations, provides a high-level view of the device pin muxing and can be used to determine the possible mix of peripheral options for a specific application. b. emifa/vpss block major configuration choices: the emifa/vpss block features extensive pin multiplexing to accommodate a variety of applications. in addition to figure 3-10 , section 3.7.3.11 , emifa/vpss block muxing, provides more details on the major configuration choices for this block. 2. see section 3.7.3.1 , multiplexed pins on dm6431, for a summary of all the multiplexed pins on this device and the pin mux group they belong to. 3. refer to the individual pin mux sections (section 3.7.3.3 , host block muxing to section 3.7.3.11 , emifa/vpss block muxing) for pin muxing details for a specific pin mux block. a. for peripherals that span multiple pin mux blocks, the user must select the appropriate pins for that peripheral in all relevant pin mux blocks. for more details, see section 3.7.3.2 , peripherals spanning multiple pin mux blocks. for details on pinmux0 and pinmux1 registers, see section 3.7.2 . table 3-20 summarizes all of the multiplexed pins on dm6431, the pin mux group for each pin, and the pinmux register fields that control the pin. for pin mux details, see the specific pin mux group section (section 3.7.3.3 , host block muxing to section 3.7.3.11 , emifa/vpss block muxing). for a description of the pinmux register fields, see section 3.7.2 . submit documentation feedback device configurations 87
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-20. multiplexed pins on dm6431 signal pinmux description zwt zdu name pinmux group controlled by pinmux bit fields no. no. pclk/gp[54] a14 a18 emifa/vpss sub-block 0 ccdcsel vd/gp[53] a13 a17 emifa/vpss sub-block 0 hvdsel hd/gp[52] a15 a19 emifa/vpss sub-block 0 hvdsel em_a[13]/gp[51] b10 a12 emifa/vpss sub-block 0 aem, aeaw em_a[14]/gp[50] a10 a13 emifa/vpss sub-block 0 aem, aeaw em_a[15]/gp[49] b11 c13 emifa/vpss sub-block 0 aem, aeaw em_a[16]/gp[48] c11 b13 emifa/vpss sub-block 0 aem, aeaw em_a[17]/gp[47] a11 b14 emifa/vpss sub-block 0 aem, aeaw em_a[18]/gp[46] d11 a14 emifa/vpss sub-block 0 aem, aeaw ci1(ccd9)/em_a[19]/gp[45] b12 c14 emifa/vpss sub-block 0 aem, aeaw, ci10sel ci0(ccd8)/em_a[20]/gp[44] c12 c15 emifa/vpss sub-block 0 aem, aeaw, ci10sel yi7(ccd7)/gp[43] a12 a15 emifa/vpss sub-block 0 ccdcsel yi6(ccd6)/gp[42] b13 b15 emifa/vpss sub-block 0 ccdcsel yi5(ccd5)/gp[41] c13 b16 emifa/vpss sub-block 0 ccdcsel yi4(ccd4)/gp[40] d14 c18 emifa/vpss sub-block 0 ccdcsel yi3(ccd3)/gp[39] b14 a16 emifa/vpss sub-block 0 ccdcsel yi2(ccd2)/gp[38] c14 b17 emifa/vpss sub-block 0 ccdcsel yi1(ccd1)/gp[37] b15 b18 emifa/vpss sub-block 0 ccdcsel yi0(ccd0)/gp[36] c15 b19 emifa/vpss sub-block 0 ccdcsel c_we/em_r/ w/gp[35] d13 c17 emifa/vpss sub-block 0 aem, cwensel c_field/em_a[21]/gp[34] d12 c16 emifa/vpss sub-block 0 aem, cfldsel em_cs5/gp[33] f19 j22 emifa/vpss sub-block 1 cs5sel em_cs4/gp[32] e19 h22 emifa/vpss sub-block 1 cs4sel gp[31] d19 g22 emifa/vpss sub-block 1 gp[30] g19 k22 emifa/vpss sub-block 1 gp[29] h15 k21 emifa/vpss sub-block 1 gp[28] h16 j21 emifa/vpss sub-block 1 gp[31:22] are standalone pins. they are not muxed with any other functions, but gp[27] h17 l19 emifa/vpss sub-block 1 they are included in this table because gp[26]/(fastboot) g17 k19 emifa/vpss sub-block 1 they are grouped in the emifa/vpss sub-block 1. gp[25]/(bootmode3) g16 h21 emifa/vpss sub-block 1 gp[24]/(bootmode2) g15 l20 emifa/vpss sub-block 1 gp[23]/(bootmode1) f15 k20 emifa/vpss sub-block 1 gp[22]/(bootmode0) f18 j20 emifa/vpss sub-block 1 em_d[7]/gp[21] f17 h20 emifa/vpss sub-block 1 aem em_d[6]/gp[20] f16 f21 emifa/vpss sub-block 1 aem em_d[5]/gp[19] e17 f22 emifa/vpss sub-block 1 aem em_d[4]/gp[18] e18 g21 emifa/vpss sub-block 1 aem em_d[3]/gp[17] e16 f20 emifa/vpss sub-block 1 aem em_d[2]/gp[16] d17 e22 emifa/vpss sub-block 1 aem em_d[1]/gp[15] d18 g20 emifa/vpss sub-block 1 aem em_d[0]/gp[14] d16 e21 emifa/vpss sub-block 1 aem em_cs3/gp[13] c18 d22 emifa/vpss sub-block 1 cs3sel em_cs2/gp[12] c19 c22 emifa/vpss sub-block 1 aem em_a[3]/gp[11] b18 d21 emifa/vpss sub-block 1 aem em_a[4]/gp[10]/(aeaw2/pllms2) a17 b21 emifa/vpss sub-block 1 aem device configurations 88 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-20. multiplexed pins on dm6431 (continued) signal pinmux description zwt zdu name pinmux group controlled by pinmux bit fields no. no. em_a[1]/(ale)/gp[9]/ a16 b20 emifa/vpss sub-block 1 aem (aeaw1/pllms1) em_a[2]/(cle)/gp[8]/ b16 a20 emifa/vpss sub-block 1 aem (aeaw0/pllms0) em_a[0]/gp[7]/(aem2) b17 c21 emifa/vpss sub-block 1 aem em_ba[0]/gp[6]/(aem1) c17 e20 emifa/vpss sub-block 1 aem em_ba[1]/gp[5]/(aem0) c16 c20 emifa/vpss sub-block 1 aem em_a[12]/gp[89] d10 b12 emifa/vpss sub-block 3 aem em_a[11]/gp[90] c10 c12 emifa/vpss sub-block 3 aem em_a[10]/gp[91] a9 b11 emifa/vpss sub-block 3 aem em_a[9]/gp[92] d9 c11 emifa/vpss sub-block 3 aem em_a[8]/gp[93] b9 a11 emifa/vpss sub-block 3 aem em_a[7]/gp[94] c9 c10 emifa/vpss sub-block 3 aem em_a[6]/gp[95] d8 b10 emifa/vpss sub-block 3 aem em_a[5]/gp[96] b8 a10 emifa/vpss sub-block 3 aem gp[57] a7 a8 host block gp[58] c8 b9 host block gp[59] d7 c9 host block gp[60] a8 a9 host block gp[66:57] are standalone pins. they are gp[61] b7 b8 host block not muxed with any other functions, but they are included in this table because gp[62] c7 c8 host block they are grouped in the host block. gp[63] a6 a7 host block gp[64] d6 c7 host block gp[65] b6 b7 host block gp[66] a5 a6 host block mcol/gp[67] c6 c6 host block hostbk mcrs/gp[68] b5 b6 host block hostbk mtxd3/gp[69] c5 a5 host block hostbk mtxd2/gp[70] d5 c5 host block hostbk mtxd1/gp[71] b4 b4 host block hostbk mtxd0/gp[72] d4 b5 host block hostbk mtxclk/gp[73] a4 a4 host block hostbk mrxdv/gp[74] c4 d3 host block hostbk mtxen/gp[75] d3 c4 host block hostbk mrxer/gp[76] b3 b2 host block hostbk mrxclk/gp[77] a3 a3 host block hostbk mrxd0/gp[78] c3 c2 host block hostbk mrxd1/gp[79] b2 b3 host block hostbk mrxd2/gp[80] d2 c3 host block hostbk mdclk/gp[81] c1 d1 host block hostbk mrxd3/gp[82] c2 d2 host block hostbk mdio/gp[83] d1 c1 host block hostbk gp[4]/pwm1 f3 f3 pwm1block pwm1bk aclkr0/clkx0/gp[99] h1 j1 serial port sub-block 0 spbk0 afsr0/dr0/gp[100] h4 k3 serial port sub-block 0 spbk0 ahclkr0/clkr0/gp[101] j2 k1 serial port sub-block 0 spbk0 submit documentation feedback device configurations 89
3.7.3.2 peripherals spanning multiple pin mux blocks tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-20. multiplexed pins on dm6431 (continued) signal pinmux description zwt zdu name pinmux group controlled by pinmux bit fields no. no. axr0[3]/fsr0/gp[102] g4 j3 serial port sub-block 0 spbk0 axr0[2]/fsx0/gp[103] h3 j2 serial port sub-block 0 spbk0 axr0[1]/dx0/gp[104] j3 k2 serial port sub-block 0 spbk0 axr0[0]/gp[105] h2 h2 serial port sub-block 1 spbk1 aclkx0/gp[106] f1 g1 serial port sub-block 1 spbk1 afsx0/gp[107] g2 g2 serial port sub-block 1 spbk1 ahclkx0/gp[108] g1 h1 serial port sub-block 1 spbk1 amutein0/gp[109] f2 g3 serial port sub-block 1 spbk1 amute0/gp[110] g3 h3 serial port sub-block 1 spbk1 hecc_rx/tinp1l/gp[56] l4 p3 timer 1 block tim1bk hecc_tx/tout1l/gp[55] k4 n3 timer 1 block tim1bk tinp0l/gp[98] k2 l2 timer 0 block tim0bk clks0/tout0l/gp[97] j4 l3 timer 0 block tim0bk urxd0/gp[85] l2 m2 uart0 data block ur0dbk utxd0/gp[86] k3 n1 uart0 data block ur0dbk ucts0/gp[87] l1 p1 uart0 flow control block ur0fcbk urts0/pwm0/gp[88] l3 m3 uart0 flow control block ur0fcbk clkout0/pwm2/gp[84] m1 r1 clkout block ckobk note: pinmux group emifa/vpss sub-block 2 is not shown in the above table because there is no actual pin multiplexing in that block. but this block is still considered a "pin mux block" because it contains some of the pins necessary for emifa. the pins in this block are as follows: emifa/vpss sub-block 2 ? em_wait/(rdy/ bsy) ? em_oe ? em_we some peripherals span multiple pin mux blocks. to use these peripherals, they must be selected in all of the relevant pin mux blocks. the following is the list of peripherals that span multiple pin mux blocks: mcbsp0: six mcbsp0 pins are located in the serial port sub-block 0, but the clks0 pin is muxed in the timer0 block. to select mcbsp0 pins, program pinmux registers as follows: ? serial port sub-block 0: spbk0 = 01 ? timer0 block: if clks0 pin is desired, program tim0bk = 10 or 11. uart0: the two uart0 data pins are located in the uart0 data block, but the two uart0 flow control pins are located in the uart0 flow control block. to select uart0, program pinmux registers as follows: ? uart0 data block: ur0bk = 1 ? uart0 flow control block: if flow control pins are desired, program ur0fcbk = 01. device configurations 90 submit documentation feedback
3.7.3.3 host block muxing tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 this block of 27 pins consists of emac, mdio, and gpio muxed pins. the following register field selects the pin functions in the host block: pinmux1.hostbk table 3-21 summarizes the 27 pins in the host block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-21. host block muxed pins selection multiplexed functions signal name emac/mdio gpio function select function select gp[57] ? ? gp[57] gp[58] ? ? gp[58] gp[59] ? ? gp[59] gp[60] ? ? gp[60] gp[61] ? ? gp[61] ? (1) gp[62] ? ? gp[62] gp[63] ? ? gp[63] gp[64] ? ? gp[64] gp[65] ? ? gp[65] gp[66] ? ? gp[66] mcol/gp[67] mcol gp[67] mcrs/gp[68] mcrs gp[68] mtxd3/gp[69] mtxd3 gp[69] mtxd2/gp[70] mtxd2 gp[70] mtxd1/gp[71] mtxd1 gp[71] mtxd0/gp[72] mtxd0 gp[72] mtxclk/gp[73] mtxclk gp[73] mrxdv/gp[74] mrxdv gp[74] mtxen/gp[75] mtxen hostbk = 100 gp[75] hostbk = 000 mrxer/gp[76] mrxer gp[76] mrxclk/gp[77] mrxclk gp[77] mrxd0/gp[78] mrxd0 gp[78] mrxd1/gp[79] mrxd1 gp[79] mrxd2/gp[80] mrxd2 gp[80] mdclk/gp[81] mdclk gp[81] mrxd3/gp[82] mrxd3 gp[82] mdio/gp[83] mdio gp[83] (1) gp[66:57] are standalone pins. they are not muxed with any other functions, but they are included in this table because they are grouped in the host block. submit documentation feedback device configurations 91
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-22 provides a different view of the host block pin muxing, showing the host block function based on pinmux1 settings. the selection options are also shown pictorially in figure 3-10 . if emac operation is desired, emac must be placed in reset before programming pinmux1.hostbk to select emac pins. table 3-22. host block function selection pinmux1 setting block function resulting pin functions hostbk gpio (27) 000 gpio: gp[83:57] ( default) 001 reserved reserved 010 reserved reserved 011 reserved reserved emac (mii): txclk, crs, col, txd[3:0], rxdv, txen, rxer, rxclk, rxd[3:0] mdio: mdc, mdio 100 emac (mii) + mdio + gpio (10) gpio: gp[66:57] if emac operation is desired, emac must be placed in reset before programming pinmux1.hostbk to select emac pins. 101 to 111 reserved reserved the vdd3p3v_pwdn.host field determines the power state of the host block pins. the host block pins default to powered up. for more details on the vdd3p3v_pwdn.host field, see section 3.2 , power considerations. device configurations 92 submit documentation feedback
3.7.3.4 uart0 data block muxing 3.7.3.5 uart0 flow control block tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 this block of 2 pins consists of uart0 data and gpio muxed pins. the pinmux1.ur0dbk register field select the pin functions in the uart0 data block. table 3-23 summarizes the 2 pins in the uart0 data block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-23. uart0 data block muxed pins selection multiplexed functions signal uart0 gpio name function select function select urxd0/gp[85] urxd0 gp[85] ur0dbk = 1 ur0dbk = 0 utxd0/gp[86] utxd0 gp[86] as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, the uart0 pins span across two pin mux blocks: uart0 data block, and uart0 flow control block. for proper uart0 operation, the two pins in the uart0 data block must be configured for uart0 data functions. the two pins in the uart0 flow control block are optional. table 3-24 provides a different view of the uart0 data block pin muxing, showing the uart0 data block function based on pinmux1.ur0dbk setting. the selection options are also shown pictorially in figure 3-10 . table 3-24. uart0 data block function selection pinmux1.ur0dbk block function resulting pin functions 0 gpio (2) ( default) gpio: gp[86:85] 1 uart0 data uart0: urxd0, utxd0 in addition, the vdd3p3v_pwdn.ur0dat field determines the power state of the uart0 data block pins. the uart0 data block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.ur0dat = 0 to power up the pins. for more details on the vdd3p3v_pwdn.ur0dat field, see section 3.2 , power considerations. the uart0 data block features internal pullup resistors, which matches the uart inactive polarity. this block of 2 pins consists of uart0 flow control, pwm0, and gpio muxed pins. the pinmux1.ur0fcbk register field selects the pin functions in the uart0 flow control block. table 3-25 summarizes the 2 pins in the uart0 flow control block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-25. uart0 flow control block muxed pins selection multiplexed functions signal uart0 pwm0 gpio name function select function select function select ucts0/ ucts0 ? ? gp[87] ur0fcbk = 00/10 gp[87] ur0fcbk = 01 urts0/ pwm0/ urts0 pwm0 ur0fcbk = 10 gp[88] ur0fcbk = 00 gp[88] submit documentation feedback device configurations 93
3.7.3.6 timer0 block tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, the uart0 pins span across two pin mux blocks: uart0 data block, and uart0 flow control block. for proper uart0 operation, the two pins in the uart0 data block must be configured for uart0 data functions. the two pins in the uart0 flow control block are optional. table 3-26 provides a different view of the uart0 flow control block pin muxing, showing the uart0 flow control block function based on pinmux1.ur0fcbk setting. the selection options are also shown pictorially in figure 3-10 . table 3-26. uart0 flow control block function selection pinmux1.ur0fcbk block function resulting pin functions 00 gpio (2) ( default) gpio: gp[88:87] 01 uart0 flow control uart0: ucts0, urts0 pwm0: pwm0 10 pwm0 + gpio (1) gpio: gp[87] 11 reserved reserved in addition, the vdd3p3v_pwdn.ur0fc field determines the power state of the uart0 flow control block pins. the uart0 flow control block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.ur0fc = 0 to power up the pins. for more details on the vdd3p3v_pwdn.ur0fc field, see section 3.2 , power considerations. the uart0 flow control block features internal pullup resistors, which matches the uart inactive polarity. this block of 2 pins consists of timer0, mcbsp0, and gpio muxed pins. the pinmux1.tim0bk register field selects the pin functions in the timer0 block. table 3-27 summarizes the 2 pins in the timer0 block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-27. timer0 block muxed pins selection multiplexed functions signal mcbsp timer0 gpio name function select function select function select tinp0l/ ? ? tinp0l tim0bk = 01/11 gp[98] gp[98] tim0bk = 00 clks0/ tout0l/ clks0 tim0bk = 11 tout0l tim0bk = 01 gp[97] gp[97] as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, the mcbsp0 pins span across two pin mux blocks: serial port sub-block0, and timer0 block. for proper mcbsp0 operation, the serial port sub-block0 must be programmed to select mcbsp0 function. the mcbsp0 clks0 pin in the timer0 block is optional for mcbsp0 operation. clks0 is only needed if you desire using clks0 as an external clock source to the mcbsp0 internal sample rate generator. table 3-28 provides a different view of the timer0 block pin muxing, showing the timer0 block function based on pinmux1.tim0bk setting. the selection options are also shown pictorially in figure 3-10 . device configurations 94 submit documentation feedback
3.7.3.7 timer1 block tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-28. timer0 block function selection pinmux1.tim0bk block function resulting pin functions 00 gpio (2) ( default) gpio: gp[98:97] 01 timer0 timer0: tinp0l, tout0l 10 reserved ? mcbsp0 external clock source, mcbsp0: clks0 11 timer0 input timer0: tinp0l in addition, the vdd3p3v_pwdn.timer0 field determines the power state of the timer0 block pins. the timer0 block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.timer0 = 0 to power up the pins. for more details on the vdd3p3v_pwdn.timer0 field, see section 3.2 , power considerations. this block of 2 pins consists of timer1, hecc, and gpio muxed pins. the pinmux1.tim1bk register field selects the pin functions in the timer1 block. table 3-29 summarizes the 2 pins in the timer1 block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-29. timer1 block muxed pins selection multiplexed functions signal hecc timer1 gpio name function select function select function select hecc_rx/ tinp1l/ hecc_rx tinp1l gp[56] gp[56] tim1bk = 11 tim1bk = 01 tim1bk = 00 hecc_tx/ tout1l/ hecc_tx tout1l gp[55] gp[55] table 3-30 provides a different view of the timer1 block pin muxing, showing the timer1 block function based on pinmux1.tim1bk setting. the selection options are also shown pictorially in figure 3-10 . table 3-30. timer1 block function selection pinmux1.tim1bk block function resulting pin functions 00 gpio (2) ( default) gpio: gp[56:55] 01 timer1 timer1: tinp1l, tout1l 10 reserved ? 11 hecc hecc: hecc_rx, hecc_tx in addition, the vdd3p3v_pwdn.timer1 field determines the power state of the timer1 block pins. the timer1 block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.timer1 = 0 to power up the pins. for more details on the vdd3p3v_pwdn.timer1 field, see section 3.2 , power considerations. the timer1 block features internal pull up resistors, which matches the hecc inactive polarity. submit documentation feedback device configurations 95
3.7.3.8 serial port block tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com this block of 12 pins consists of mcasp0, mcbsp0, and gpio muxed pins. the following register fields select the pin functions in the serial port block: pinmux1.spbk0 pinmux1.spbk1 the serial port block is further subdivided into these sub-blocks: serial port sub-block 0: mcbsp0, part of mcasp0, and gpio. serial port sub-block 1: part of mcasp0 and gpio. table 3-31 summarizes the 12 pins in the serial port block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-31. serial port block muxed pins selection multiplexed functions signal name mcasp0 mcbsp0 gpio function select function select function select serial port sub-block 0 aclkr0/clkx0/gp[99] aclkr0 clkx0 gp[99] afsr0/dr0/gp[100] afsr0 dr0 gp[100] ahclkr0/clkr0/gp[101] ahclkr0 clkr0 gp[101] spbk0 = 10 spbk0 = 01 spbk0 = 00 axr0[3]/fsr0/gp[102] axr0[3] fsr0 gp[102] axr0[2]/fsx0/gp[103] axr0[2] fsx0 gp[103] axr0[1]/dx0/gp[104] axr0[1] dx0 gp[104] serial port sub-block 1 axr0[0]/gp[105] axr0[0] ? ? gp[105] aclkx0/gp[106] aclkx0 ? ? gp[106] afsx0/gp[107] afsx0 ? ? gp[107] spbk1 = 10 spbk1 = 00 ahclkx0/gp[108] ahclkx0 ? ? gp[108] amutein0/gp[109] amutein0 ? ? gp[109] amute0/gp[110] amute0 ? ? gp[110] as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, the mcbsp0 pins span across two pin mux blocks: serial port sub-block0, and timer0 block. for proper mcbsp0 operation, the serial port sub-block0 must be programmed to select mcbsp0 function. the mcbsp0 clks0 pin in the timer0 block is optional for mcbsp0 operation. clks0 is only needed if you desire using clks0 as an external clock source to the mcbsp0 internal sample rate generator. table 3-32 and table 3-33 provide a different view of the serial port block. table 3-32 shows the serial port sub-block 0 function based on pinmux1.spbk0 setting. table 3-33 shows the serial port sub-block 1 function based on pinmux1.spbk1 setting. these selection options are also shown pictorially in figure 3-10 . table 3-32. serial port sub-block 0 function selection pinmux1.spbk0 block function resulting pin functions 00 gpio (6) ( default) gpio: gp[104:99] 01 mcbsp0 mcbsp0: clkx0, fsx0, dx0, clkr0, fsr0, dr0 mcasp0: aclkr0, afsr0, ahclkr0, axr0[3], 10 mcasp0 receive, 3 serializers axr0[2], axr0[1] 11 reserved reserved device configurations 96 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-33. serial port sub-block 1 function selection pinmux1.spbk1 block function resulting pin functions 00 gpio (6) ( default) gpio: gp[110:105] 01 reserved ? mcasp0 transmit with 1 serializer and mcasp0: axr0[0], aclkx0, afsx0, ahclkx0, 10 mute control amutein0 (1) , amute0 11 reserved ? (1) the input from the amutein0/gp[109] pin is connected to both the mcasp0 and gpio. in addition, the vdd3p3v_pwdn.sp field determines the power state of the serial port block pins. the serial port block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.sp = 0 to power up the pins. for more details on the vdd3p3v_pwdn.sp field, see section 3.2 , power considerations. to facilitate mcasp0 operation, the input from the amutein0/gp[109] pin is connected to both the mcasp0 and the gpio module. therefore when an external mute event occurs, in addition to notifying the mcasp0, it can also cause an interrupt through the gpio module. submit documentation feedback device configurations 97
3.7.3.9 pwm1 block tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com this block of 1 pin consists of pwm1 and gpio muxed pins (gp[4]/pwm1). the pinmux1.pwm1bk register field selects the pin function in the pwm1 block. table 3-34 summarizes the 1 pin in the pwm1 block, its multiplexed function, and the pinmux configurations to select the corresponding function. table 3-34. pwm1 block muxed pin selection multiplexed functions signal pwm1 gpio name function select function select gp[4]/pwm1 pwm1 pwm1bk = 1 gp[4] pwm1bk = 0 table 3-35 provides a different view of the pwm1 block pin muxing, showing the pwm1 block function based on pinmux1.pwm1bk setting. the selection options are also shown pictorially in figure 3-10 . table 3-35. pwm1 block function selection pinmux1.pwm1bk block function resulting pin functions 0 gpio (1) ( default) gpio: gp[4] 1 pwm1 pwm1: pwm1 in addition, the vdd3p3v_pwdn.pwm1 field determines the power state of the pwm1 block pin. the pwm1 block pin defaults to powered down and not operational. to use this pin, user must first program vdd3p3v_pwdn.pwm1 = 0 to power up the pin. for more details on the vdd3p3v_pwdn.pwm1 field, see section 3.2 , power considerations. device configurations 98 submit documentation feedback
3.7.3.10 clkout block 3.7.3.11 emifa/vpss block muxing tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 this block of 1 pin consists of clkout, pwm2, and gpio muxed pin (clkout0/pwm2/gp[84]). the pinmux1.ckobk register field selects the pin function in the clkout block. table 3-36 summarizes the 1 pin in the clkout block, its multiplexed function, and the pinmux configurations to select the corresponding function. table 3-36. clkout block multiplexed pin selection multiplexed functions signal clkout0 pwm2 gpio name function select function select function select clkout0/ pwm2/ clkout0 ckobk = 01 pwm2 ckobk = 10 gp[84] ckobk = 00 gp[84] table 3-37 provides a different view of the clkout block pin muxing, showing the clkout block function based on pinmux1.ckobk setting. the selection options are also shown pictorially in figure 3-10 . table 3-37. clkout block function selection pinmux1.ckobk block function resulting pin functions 00 gpio (1) gpio: gp[84] 01 clkout ( default) device clock-out: clkout0 10 pwm2 pwm2: pwm2 11 reserved reserved this block defaults to clkout0 pin function. in addition, the vdd3p3v_pwdn.clkout field determines the power state of the clkout block pin. the clkout block pin defaults to powered up. for more details on the vdd3p3v_pwdn.clkout field, see section 3.2 , power considerations. this block of 61 pins consists of vpss, emifa, and gpio muxed pins. the following register fields affect the pin functions in the emifa/vpss block: all pinmux0 register fields: aem, cs5sel, cs4sel, cs3sel, aeaw, ccdcsel, hvdsel, cwensel, cfldsel, and ci10sel the emifa/vpss block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to accommodate a wide variety of applications: sub-block 0: multiplexed between vpfe, emifa address/control pins, and gpio. sub-block 1: multiplexed between emifa data/address/control pins, and gpio. sub-block 2: no multiplexing. emifa control pins em_wait/(rdy/ bsy), em_oe, em_we. sub-block 3: multiplexed between emifa address pins em_a[12:6] and gpio. the embk0, embk1, embk2, embk3 fields in the vdd3p3v_pwdn register determine the power state of the emifa/vpss block pins. the emifa/vpss block pins default to powered up. for more details on the embk0, embk1, embk2, embk3 fields in the vdd3p3v_pwdn register, see section 3.2 , power considerations. to understand pin multiplexing in the emifa/vpss block, the user should start with section 3.7.3.11.1 , emifa/vpss block pin selection procedure, which outlines the procedures to select pin functions of this block. section 3.7.3.11.7 , emifa/vpss block pin-by-pin multiplexing summary, provides a pin-by-pin multiplexing summary for the emifa/vpss block. for more information on the pinmux0 and pinmux1 registers, see section 3.7.2 , pin muxing selection after device reset. submit documentation feedback device configurations 99
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com 3.7.3.11.1 emifa/vpss block pin selection procedure follow the steps below to perform pin selection for the emifa/vpss block and its sub-blocks. 1. major configuration options: start with table 3-38 , emifa/vpss block major configuration choices. based on the peripheral needs, the user should select from the major configuration options in this block: major config options a, b, and e. 2. sub-block 2 and sub-block 3 selection: after selecting the major configuration option from table 3-38 , emifa/vpss block major configuration choices, the pin selection for sub-block 2 and sub-block 3 is complete. 3. sub-block 0 selection: use table 3-39 through table 3-41 , emifa/vpss sub-block 0 configuration choices, to refine sub-block 0 pin selections. a. go to the table with the major configuration option chosen in step 1. b. each major configuration option is further divided down into multiple minor configuration options. select a minor configuration option that best suits the application need. c. within the chosen minor configuration option, further refine the detailed pin configurations by selecting the settings of pinmux0 fields ccdcsel, hvdsel, cwensel, cfldsel, and ci10sel. d. the selection fields columns show the settings needed to program the pinmux0 register. 4. sub-block 1 selection: use table 3-42 through table 3-44 , emifa/vpss sub-block 1 configuration choices, to refine sub-block 1 pin selection. a. go to the table with the major configuration option chosen in step 1. b. each major configuration option is further divided down into multiple minor configuration options. select a minor configuration option that best suits the application need. c. within the chosen minor configuration option, further refine the detailed pin configurations by selecting the settings of pinmux0 fields cs3sel, cs4sel, and cs5sel. d. the selection fields columns show the settings needed to program the pinmux0 register. after following the procedure in this section to determine pin functions for the emifa/vpss block, the user should refer to section 3.7.3.11.7 , emifa/vpss block pin-by-pin multiplexing summary, for pin-multiplexing information on a pin-by-pin basis. 3.7.3.11.2 emifa/vpss block major configuration choices table 3-38 shows the major configuration choices in the emifa/vpss block. for instructions on how to use the emifa/vpss block major configuration choices table for the emifa/vpss block and sub-blocks, see section 3.7.3.11.1 . device configurations 100 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-38. emifa/vpss block major configuration choices pinmux selection resulting peripherals/pins major fields (1) config. # gp pins vpfe and # gp pins option aem ccdcsel emifa (from gp[33:5]) (from gp[54:34]) # gp pins ccdcsel vpfe & # gp pins no ccdc 0 21 gp pins a 000 0, 1 - 29 gp pins 8-to-10-bit ccdc 1 6-to-12 gp pins no ccdc 8-bit emifa (async) 0 11-to-19 gp pins pinout mode 1 with b 001 (2) 0, 1 9-to-13 gp pins address pins to support 8-to-10-bit ccdc (2) 1 (2) 32kb to 16mb per cs. 0-to-10 gp pins no ccdc 0 21 gp pins 8-bit emifa (nand) e 101 0, 1 14-to-18 gp pins pinout mode 5 8-to-10-bit ccdc 1 6-to-12 gp pins (1) for additional pin mux details for each sub-block, see table 3-39 through table 3-41 , emifa/vpss sub-block 0 configuration choices, and table 3-42 through table 3-44 , emifa/vpss sub-block 1 configuration choices. (2) if pinmux0.aem = 001, it is not possible to get the c_we pin for vpfe. as shown in table 3-38 , the major configuration choices of the emifa/vpss block are determined by the following pinmux register fields: pinmux0 register fields aem and ccdcsel based on the peripheral needs, select from the major configuration options in this block: major configuration options a, b, and e. the following is an example on how to read table 3-38 . for example, the "pinmux selection fields" columns indicate that major configuration choice b is selected through setting pinmux0.aem = 1 and ccdcsel = 0 or 1 (based on the system's vpfe requirement). the "resulting peripherals/pins" columns indicate that major configuration option b can support the following combination of pin functions: pins for 8-bit emifa (async or nand) function. the number of address pins supported provide 32kbyte to 16mbyte address reach per emifa chip select (cs) space. pins for up to 10-bit vpfe. if 8-to-10-bit vpfe (ccdcsel = 1) is selected, the user may have 0 to 10 gpio pins. exact detail on number of gpio pins and vpfe control pins is furthered determined by other pinmux0 settings discussed in the emifa/vpss sub-block 0 configuration choices. 9-to-13 gpio pins from gp[33:5]. for details on the number of gpio pins, see section 3.7.3.11.4 , emifa/vpss sub-block 1 configuration choices. after using table 3-38 to select the major configuration option for the emifa/vpss block, proceed to select the detailed pin choices in the emifa/vpss sub-blocks. submit documentation feedback device configurations 101
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com 3.7.3.11.3 emifa/vpss sub-block 0 configuration choices table 3-39 through table 3-41 show the configuration choices in the emifa/vpss sub-block 0. for instructions on how to use the different configuration choices tables for the emifa/vpss block and sub-blocks, see section 3.7.3.11.1 . note: italics in these tables indicate mandatory settings for a given minor configuration option. before using table 3-39 through table 3-41 to configure the details of the emifa/vpss sub-block 0, the user should first select a major configuration option for the emifa/vpss block (see section 3.7.3.11.2 ). after determining the major configuration option (a, b, or e), the user can now use table 3-39 through table 3-41 to refine sub-block 0 pin selections: 1. go to the table with the major configuration option chosen from table 3-38 . 2. each major configuration option is further divided down into multiple minor configuration options. select a minor configuration option that best suits the application need. 3. within the chosen minor configuration option, further refine the detailed pin configurations by selecting the settings of pinmux0 fields ccdcsel, hvdsel, cwensel, cfldsel, and ci10sel. 4. the pinmux selection fields columns show the settings needed to program the pinmux0 register. table 3-39. emifa/vpss sub-block 0 configuration choice a (1) major minor pinmux selection fields resulting peripherals/pins config config aem aeaw others emifa vpfe # gpio pins option option cfg summary no emifa no ccdc 21 gp pins basic pins you get gp[51:46] ccdcsel = 0 0 = gp[54, 43:36] a1 000 000 hvdsel = 0 0 = gp[53:52] - - cwensel = 0 0 = gp[35] cfldsel = 0 0 = gp[34] ci10sel = 0 0 = gp[45:44] a cfg summary no emifa 8-to-10-bit ccdc 6-to-12 gp pins basic pins you get - gp[51:46] ccdcsel = 1 1 = pclk, yi[7:0] - a2 000 000 hvdsel = 0,1 1 = vd, hd 0 = gp[53:52] - cwensel = 0,1 1 = c_we 0 = gp[35] cfldsel = 0,1 1 = c_field 0 = gp[34] ci10sel = 0,1 1 = ci[1:0] 0 = gp[45:44] (1) italics indicate mandatory settings for a given minor configuration option. 102 device configurations submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-40. emifa/vpss sub-block 0 configuration choice b (1) major minor pinmux selection fields resulting peripherals/pins config config aem aeaw others emifa vpfe # gpio pins option option 8-bit emifa (async) pinout config summary no ccdc 11 gp pins mode 1 w/ em_a[21:0] basic pins you get em_a[18:13] - b b1 001 100 ccdcsel = 0 - 0 = gp[54, 43:36] hvdsel = 0 - 0 = gp[53:52] - cwensel = 0 0 = em_r/ w - cfldsel = 0 0 = em_a21 - ci10sel = 0 0 = em_a[19:20] - 8-bit emifa (async) pinout config summary 8-to-10-bit ccdc 6-to-10 gp pins mode 1 w/ em_a[12:0] only basic pins you get - - gp[51:46] ccdcsel = 1 - 1 = pclk, yi[7:0] - b b2 001 000 hvdsel = 0,1 - 1 = vd, hd 0 = gp[53:52] cwensel = 0 0 = em_r/ w - - 0 = em_a21 cfldsel = 0,1 1 = c_field - (not used) ci10sel = 0,1 - 1 = ci[1:0] 0 = gp[45:44] 8-bit emifa (async) pinout config summary 8-to-10-bit ccdc 4-to-8 gp pins mode 1 w/ em_a[14:0] only basic pins you get em_a[13:14] - gp[49:46] ccdcsel = 1 - 1 = pclk, yi[7:0] - b b3 001 001 hvdsel = 0,1 - 1 = vd, hd 0 = gp[53:52] cwensel = 0 0 = em_r/ w - - 0 = em_a21 cfldsel = 0,1 1 = c_field - (not used) ci10sel = 0,1 - 1 = ci[1:0] 0 = gp[45:44] 8-bit emifa (async) pinout config summary 8-to-10-bit ccdc 2-to-6 gp pins mode 1 w/ em_a[16:0] only basic pins you get em_a[16:13] - gp[47:46] ccdcsel = 1 - 1 = pclk, yi[7:0] - b b4 001 010 hvdsel = 0,1 - 1 = vd, hd 0 = gp[53:52] cwensel = 0 0 = em_r/ w - - 0 = em_a21 cfldsel = 0,1 1 = c_field - (not used) ci10sel = 0,1 - 1 = ci[1:0] 0 = gp[45:44] (1) italics indicate mandatory settings for a given minor configuration option. submit documentation feedback device configurations 103
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-40. emifa/vpss sub-block 0 configuration choice b (continued) major minor pinmux selection fields resulting peripherals/pins config config aem aeaw others emifa vpfe # gpio pins option option 8-bit emifa (async) pinout config summary 8-to-10-bit ccdc 0-to-4 gp pins mode 1 w/ em_a[18:0] only basic pins you get em_a[18:13] - - ccdcsel = 1 - 1 = pclk, yi[7:0] - b b5 001 011 hvdsel = 0,1 - 1 = vd, hd 0 = gp[53:52] cwensel = 0 0 = em_r/ w - - 0 = em_a21 cfldsel = 0,1 1 = c_field - (not used) ci10sel = 0,1 - 1 = ci[1:0] 0 = gp[45:44] 8-bit emifa (async) pinout config summary 8-bit ccdc 0-to-2 gp pins mode 1 w/ em_a[21:0] basic pins you get em_a[18:13] - - b b6 001 100 ccdcsel = 1 - 1 = pclk, yi[7:0] - hvdsel = 0,1 - 1 = vd, hd 0 = gp[53:52] cwensel = 0 0 = em_r/ w - - cfldsel = 0,1 0 = em_a21 1 = c_field - ci10sel = 0 0 = em_a[19:20] - - device configurations 104 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-41. emifa/vpss sub-block 0 configuration choice e (1) major minor pinmux selection fields resulting peripherals/pins config config aem aeaw others emifa vpfe # gpio pins option option 8-bit emifa cfg summary (nand) pinout no ccdc 21 gp pins mode 5 basic pins you get - - gp[51:46] ccdcsel = 0 0 = gp[54, 43:36] e1 101 000 hvdsel = 0 0 = gp[53:52] cwensel = 0 - - 0 = gp[35] cfldsel = 0 0 = gp[34] ci10sel = 0 0 = gp[45:44] e 8-bit emifa cfg summary (nand) pinout 8-to-10-bit ccdc 6-to-12 gp pins mode 5 basic pins you get - - gp[51:46] ccdcsel = 1 1 = pclk, yi[7:0] - e2 101 000 hvdsel = 0,1 1= vd, hd 0 = gp[53:52] cwensel = 0,1 - 1 = c_we 0 = gp[35] cfldsel = 0,1 1 = c_field 0 = gp[34] ci10sel = 0,1 1 = ci[1:0] 0 = gp[45:44] (1) italics indicate mandatory settings for a given minor configuration option. as shown in table 3-39 through table 3-41 , the configuration choices of the emifa/vpss sub-block 0 are determined by the following pinmux register fields: pinmux0 register fields aem, aeaw, ccdcsel, hvdsel, cwensel, cfldsel, and ci10sel. the following is an example of how to read table 3-39 through table 3-41 using sub-block 0 minor configuration b6 as an example: the pinmux selection fields columns indicate that sub-block 0 minor configuration option b6 is selected through setting, pinmux0.aem = 1, pinmux0.aeaw = 4, ccdcsel = 1, hvdsel = 0 or 1 (based on the system?s need for vpfe control signals vd and hd), cwensel = 0 (mandatory setting), cfldsel = 0 or 1 (based on the system?s need for vpfe control signal c_field), and ci10sel = 0 (mandatory). the resulting peripherals/pins columns show the functional pins resulting from the pinmux setting. for example, pinmux0.ccdcsel = 1 gives the user the pclk and yi[7:0] pins for the vpfe. pinmux0.hvdsel = 1 gives the user vd and hd pins for vpfe, while hvdsel = 0 gives the user 2 gp pins. submit documentation feedback device configurations 105
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com 3.7.3.11.4 emifa/vpss sub-block 1 configuration choices table 3-42 through table 3-44 show the configuration choices in the emifa/vpss sub-block 1. for instructions on how to use the different configuration choices tables for the emifa/vpss block and sub-blocks, see section 3.7.3.11.1 , emifa/vpss block pin selection procedure. before using table 3-42 through table 3-44 to configure the details of the emifa/vpss sub-block 1, the user should first select the major configuration option for the emifa/vpss block (see section 3.7.3.11.2 , emifa/vpss block major configuration choices). after determining the major configuration option (a, b, or e), the user can now use table 3-42 through table 3-44 to refine the sub-block 1 pin selections. 1. go to the table with the major configuration option chosen from table 3-38 . 2. each major configuration option is further divided down into multiple minor configuration options. select a minor configuration option that best suits the application need. 3. within the chosen minor configuration option, further refine the detailed pin configurations by selecting the settings of pinmux0 fields cs3sel, cs4sel, and cs5sel. 4. the pinmux selection fields columns give the user the settings needed to program the pinmux0 register. table 3-42. emifa/vpss sub-block 1 configuration choice a (1) major minor pinmux selection fields resulting peripherals/pins config config aem others emifa gpio option option cfg summary no emifa 29 gp pins cs3sel = 0 a a1 000 cs4sel = 0 - 0 = gp[33:5] cs5sel = 0 (1) italics indicate mandatory settings for a given minor configuration option. table 3-43. emifa/vpss sub-block 1 configuration choice b (1) major minor pinmux selection fields resulting peripherals/pins config config aem others emifa gpio option option 8-bit emifa (async) cfg summary 10-to-13 gp pins pinout mode 1 em_d[7:0], em_cs2, basic pins you get 0 = gp[31:22] em_a[4:0], em_ba[1:0] b b1 001 cs3sel = 0,1 1 = em_cs3 0 = gp[13] cs4sel = 0,1 1 = em_cs4 0 = gp[32] cs5sel = 0,1 1 = em_cs5 0 = gp[33] (1) italics indicate mandatory setting for a given minor configuration option. table 3-44. emifa/vpss sub-block 1 configuration choice e (1) major minor pinmux selection fields resulting peripherals/pins config config aem others emifa gpio option option 8-bit emifa (nand) cfg summary 15-to-18 gp pins pinout mode 5 basic pins you get em_d[7:0], em_a[2:1], em_cs2 0 = gp[31:22, 11:10, 7:5] e e1 101 cs3sel = 0,1 1 = em_cs3 0 = gp[13] cs4sel = 0,1 1 = em_cs4 0 = gp[32] cs5sel = 0,1 1 = em_cs5 0 = gp[33] (1) italics indicate mandatory setting for a given minor configuration option. device configurations 106 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the sub-block 1 minor configuration options are independent from the sub-block 0 minor configuration options. the user can independently select the appropriate minor configuration option for each sub-block. as shown in table 3-42 through table 3-44 , the configuration choices of the emifa/vpss sub-block 1 are determined by the following pinmux register fields: pinmux0 register fields aem, cs3sel, cs4sel, and cs5sel. the following is an example on how to read table 3-42 through table 3-44 using sub-block 1 minor configuration e1 as an example: the pinmux selection fields columns indicate that sub-block 1 minor configuration option e1 is selected through setting pinmux0 fields to aem = 5, cs3sel = 0/1 (based on the desired pin choice), cs4sel = 0/1 (based on the desired pin choice), and cs5sel = 0/1 (based on the desired pin choice). the resulting peripherals/pins columns show the functional pins resulting from the pinmux setting. for example, you automatically get emifa pins em_d[7:0], em_a[2:1], and em_cs2 in addition to at least 15 gpio pins in minor config option e1 (gp[31:22], gp[11:10], and gp[7:5]). if you program cs3sel = 1, cs4sel = 0, and cs5sel = 0, you also get em_cs3, gp[32], and gp[33]. 3.7.3.11.5 emifa/vpss sub-block 2 configuration choices the 3 pins in the emifa/vpss sub-block 2 are standalone (non-multiplexed) pins. they always function as emifa control pins em_wait/(rdy/ bsy), em_oe, and em_we. no pin mux selection is necessary for this sub-block. 3.7.3.11.6 emifa/vpss sub-block 3 configuration choices the 8 pins in the emifa/vpss sub-block 3 are multiplexed between: emifa address pins em_a[12:5] gpio pins gp[96:89] the pin functions in the emifa/vpss sub-block 3 are determined by the following pinmux register fields: pinmux0.aem once the major configuration option for the emifa/vpss block (see section 3.7.3.11.2 , emifa/vpss block major configuration choices) is chosen, no further actions are necessary to refine the emifa/vpss sub-block 3 pin selection. for instructions on configuring the emifa/vpss block, see section 3.7.3.11.1 , emifa/vpss block pin selection procedure. table 3-45 summarizes the pin selections in the emifa/vpss sub-block 3 based on the pinmux selections. table 3-45. emifa/vpss sub-block 3 configuration choices major pinmux selection field resulting peripherals/pins config aem emifa gpio option a 000 - gp[96:89] b 001 em_a[12:5] - e 101 - gp[96:89] the following is an example on how to read table 3-45 using sub-block 3 major configuration b as an example: the pinmux selection fields columns indicate that sub-block 3 major configuration option b is selected through setting pinmux0.aem = 001b. the resulting peripherals/pins columns show the functional pins resulting from the pinmux setting. in major configuration b, the user gets emifa address pins em_a[12:5] from sub-block 3. submit documentation feedback device configurations 107
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com 3.7.3.11.7 emifa/vpss block pin-by-pin multiplexing summary this section summarizes the emifa/vpss block muxing on a pin-by-pin basis. it provides an alternative view to pin muxing in the emifa/vpss block. this section should only be used after following the procedures listed in section 3.7.3.11.1 to determine the actual emifa/vpss configuration option for the application need. table 3-46 shows the pin multiplexing control for each pin in the emifa/vpss sub-block 0. these are the fields in the pinmux0 and pinmux1 registers that control the multiplexing in this sub-block: pinmux0: aem, aeaw, cwensel, cfldsel, ci10sel, ccdcsel, and hvdsel table 3-47 shows the pin multiplexing control for each pin in the emifa/vpss sub-block 1. these are the fields in the pinmux0 register that control the multiplexing in this sub-block: pinmux0: aem, cs5sel, cs4sel, and cs3sel emifa/vpss sub-block 2 is dedicated to emifa pins em_wait/(rdy/ bsy), em_oe, and em_we. there is no pin multiplexing in this block. these pins always function as emifa control pins. table 3-48 shows the pin multiplexing control for each pin in the emifa/vpss sub-block 3. these are the fields in the pinmux0 register that control the multiplexing in this sub-block: pinmux0: aem device configurations 108 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 3-46. emifa/vpss sub-block 0 pin-by-pin mux control multiplexed functions signal name vpfe emifa addr/ctrl gpio function select function select function select pclk/gp[54] pclk ccdcsel = 1 ? ? gp[54] ccdcsel = 0 yi7(ccd7)/gp[43] yi7(ccd7) ? ? gp[43] yi6(ccd6)/gp[42] yi6(ccd6) ? ? gp[42] yi5(ccd5)/gp[41] yi5(ccd5) ? ? gp[41] yi4(ccd4)/gp[40] yi4(ccd4) ? ? gp[40] yi3(ccd3)/gp[39] yi3(ccd3) ? ? gp[39] yi2(ccd2)/gp[38] yi2(ccd2) ? ? gp[38] yi1(ccd1)/gp[37] yi1(ccd1) ? ? gp[37] yi0(ccd0)/gp[36] yi0(ccd0) ? ? gp[36] vd/gp[53] vd hvdsel = 1 ? ? gp[53] hvdsel = 0 hd/gp[52] hd ? ? gp[52] em_a[13]/gp[51] ? ? em_a[13] aem = 1, gp[51] aem = 0/1/5, aeaw = 1/2/3/4 aeaw = 0 em_a[14]/gp[50] ? em_a[14] gp[50] em_a[15]/gp[49] ? ? em_a[15] aem = 1, gp[49] aem = 0/1/5, aeaw = 2/3/4 aeaw = 0/1 (1) em_a[16]/ gp[48] ? em_a[16] gp[48] em_a[17]/gp[47] ? ? em_a[17] aem = 1, gp[47] aem = 0/1/5, aeaw = 3/4 aeaw = 0/1/2 (1) em_a[18]/ gp[46] ? em_a[18] gp[46] ci1(ccd9)/em_a[19]/ gp[45] ci1(ccd9) aem = 0/1/5, em_a[19] aem = 1, gp[45] aem = 0/1/5, aeaw = 0/1/2/3 (1) , aeaw = 4, aeaw = 0/1/2/3 (1) , ci0(ccd8)/em_a[20]/ gp[44] ci0(ccd8) em_a[20] gp[44] ci10sel = 1 ci10sel = 0 ci10sel = 0 c_we/em_r/ w/gp[35] cwensel = 1, cwensel = 0, cwensel = 0, c_we em_r/ w gp[35] aem = 0/5 aem = 1 aem = 0/5 c_field/em_a[21]/gp[34] cfldsel = 1, cfldsel = 0, cfldsel = 0, c_field em_a[21] gp[34] aem = 0/1/5 aem = 1 aem = 0/5 (1) aeaw = 1/2/3/4 is only valid if aem[2:0] = 1. submit documentation feedback device configurations 109
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 3-47. emifa/vpss sub-block 1 pin-by-pin mux control multiplexed functions signal emifa gpio (1) name function select function select em_cs5/gp[33] em_cs5 cs5sel = 1 gp[33] cs5sel = 0 em_cs4/gp[32] em_cs4 cs4sel = 1 gp[32] cs4sel = 0 gp[31] gp[31] gp[30] gp[30] gp[29] gp[29] gp[28] gp[28] gp[27] gp[27] ? ? ? gp[26]/(fastboot) gp[26] gp[25]/(bootmode3) gp[25] gp[24]/(bootmode2) gp[24] gp[23]/(bootmode1) gp[23] gp[22]/(bootmode0) gp[22] em_d[7]/gp[21] em_d[7] gp[21] em_d[6]/gp[20] em_d[6] gp[20] em_d[5]/gp[19] em_d[5] gp[19] em_d[4]/gp[18] em_d[4] gp[18] aem = 1/5 aem = 0 em_d[3]/gp[17] em_d[3] gp[17] em_d[2]/gp[16] em_d[2] gp[16] em_d[1]/gp[15] em_d[1] gp[15] em_d[0]/gp[14] em_d[0] gp[14] em_cs3/gp[13] em_cs3 cs3sel = 1 gp[13] cs3sel = 0 em_cs2/gp[12] em_cs2 gp[12] em_a[1]/(ale)/ em_a[1]/(ale) gp[9] gp[9]/(aeaw1/pllms1) aem = 1/5 aem = 0 em_a[2]/(cle)/gp[8]/ em_a[2]/(cle) gp[8] (aeaw0/pllms0) em_a[3]/gp[11] em_a[3] gp[11] em_a[4]/gp[10]/ em_a[4] gp[10] (aeaw2/pllms2) aem = 1 aem = 0/5 em_a[0]/gp[7]/(aem2) em_a[0] gp[7] em_ba[0]/gp[6]/(aem1) em_ba[0] gp[6] em_ba[1]/gp[5]/(aem0) em_ba[1] gp[5] (1) gp[31:22] are standalone pins. they are not muxed with any other functions, but they are included in this table because they are grouped in the emifa/vpss sub-block 1. table 3-48. emifa/vpss sub-block 3 pin-by-pin mux control multiplexed functions signal name emifa gpio function select function select em_a[12]/ gp[89] em_a[12] gp[89] em_a[11]/gp[90] em_a[11] gp[90] em_a[10]/gp[91] em_a[10] gp[91] em_a[9]/gp[92] em_a[9] gp[92] aem = 1 aem = 0/5 em_a[8]/gp[93] em_a[8] gp[93] em_a[7]/gp[94] em_a[7] gp[94] em_a[6]/gp[95] em_a[6] gp[95] em_a[5]/gp[96] em_a[5] gp[96] device configurations 110 submit documentation feedback
3.8 device initialization sequence after reset tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 software should follow this initialization sequence after coming out of device reset. 1. complete the boot sequence as needed. for more details on the boot sequence, see the using the tms320dm643x bootloader application report (literature number spraag0 ). 2. if the device is not already at the desired operating frequency, program the pll controllers (pllc1 and pllc2) to configure the device frequency. for details on how to program the pllc, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). 3. program pinmux0 and pinmux1 registers to select device pin functions. for more details on programming the pinmux0 and pinmux1 registers to select device pin functions, see section 3.7 , multiplexed pin configurations. note: if emac operation is desired, the emac must be placed in reset before programming pinmux1.hostbk to select emac pins. 4. program the vdd3p3v_pwdn register to power up the necessary i/o pins. for more details on programming the vdd3p3v_pwdn register, see section 3.2 , power considerations. on dm6431, the user should program vdd3p3v_pwdn bit 13 to 1 to power down the reserved pins rsv17, rsv18, and rsv19. 5. as needed by the application, program the following system module registers when there are no active transactions on the respective peripherals: a. timerctl (section 3.6.2.1 , timer control register): applicable for timer0 and watchdog timer2 only. b. edmatccfg (section 3.6.2.2 , edma tc configuration register): applicable for edma only. the recommendation is to leave the edmatccfg register at its default. c. vpss_clkctl (section 3.3.2 , vpss clocks): applicable for vpss only. 6. program the power and sleep controller (psc) to enable the desired peripherals. for details on how to program the psc, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). 7. program the switched central resource (scr) bus priorities for the master peripherals (section 3.6.1 ). this must be configured when there are no active transactions on the respective peripherals: a. program the mstpri0 and mstpri1 registers in the system module. these registers can be programmed before or after the respective peripheral is enabled by the psc in step 6. b. program the edmacc quepri register, the c64x+ mdmaarbe.pri field, and the vpss pcr register. these registers can only be programmed after the respective peripheral is enabled by the psc in step 6. 8. configure the c64x+ megamodule and the peripherals. submit documentation feedback device configurations 111
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com a. for details on c64x+ megamodule configuration, see the tms320c64x+ dsp megamodule reference guide (literature number spru871 ). i. special considerations: bootloader disables c64x+ cache?for all boot modes that default to dspbootaddr = 0x0010 0000 (i.e., all boot modes except the emifa rom direct boot, bootmode[3:0] = 0100, fastboot = 0), the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram (l2cfg.l2mode = 0h, l1pcfg.l1pmode = 0h, and l1dcfg.l1dmode = 0h). if cache use is required, the application code must explicitly enable the cache. for more information on boot modes, see section 3.4.1 , boot modes. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). b. peripherals configuration: see the respective peripheral user?s guide. i. special considerations: ddr2 memory controller?the peripheral bus burst priority register (pbbpr) should be programmed to ensure good ddr2 throughput and to prevent command starvation (prevention of certain commands from being processed by the ddr2 memory controller). for more details, see the tms320dm643x dmp ddr2 memory controller user?s guide (literature number spru986 ). a hex value of 0x20 is recommended for the pbbpr pr_old_count field to provide a good dsp performance and still allow good utilization by other modules. 112 device configurations submit documentation feedback
3.9 debugging considerations 3.9.1 pullup/pulldown resistors tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 proper board design should ensure that input pins to the device always be at a valid logic level and not floating. this may be achieved via pullup/pulldown resistors. the features internal pullup (ipu) and internal pulldown (ipd) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. an external pullup/pulldown resistor needs to be used in the following situations: boot and configuration pins: if the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor is strongly recommended, even if the ipu/ipd matches the desired value/state. other input pins: if the ipu/ipd does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. emifa chip select outputs: on dm6431, the emifa chip select pins ( em_cs2, em_cs3, em_cs4, and em_cs5) feature an internal pulldown (ipd) resistor. if these pins are connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. for the boot and configuration pins (listed in table 2-5 , boot terminal functions), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. in addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. tips for choosing an external pullup/pulldown resistor: consider the total amount of current that may pass through the pullup or pulldown resistor. make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors. decide a target value for the net. for a pulldown resistor, this should be below the lowest v il level of all inputs connected to the net. for a pullup resistor, this should be above the highest v ih level of all inputs on the net. a reasonable choice would be to target the v ol or v oh levels for the logic family of the limiting device; which, by definition, have margin to the v il and v ih levels. select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. the current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. for bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). remember to include tolerances when selecting the resistor value. for pullup resistors, also remember to include tolerances on the dv dd rail. for most systems, a 1-k w resistor can be used to oppose the ipu/ipd while meeting the above criteria. users should confirm this resistor value is correct for their specific application. for most systems, a 20-k w resistor can be used to compliment the ipu/ipd on the boot and configuration pins while meeting the above criteria. users should confirm this resistor value is correct for their specific application. for more detailed information on input current (i i ), and the low-/high-level input voltages (v il and v ih ) for the , see section 5.3 , electrical characteristics over recommended ranges of supply voltage and operating temperature. submit documentation feedback device configurations 113
4 system interconnect 4.1 system interconnect block diagram tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com for the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table. on the dm6431 device, the c64x+ megamodule, the edma3 transfer controllers, and the system peripherals are interconnected through a switch fabric architecture (see figure 4-1 ). the switch fabric is composed of multiple switched central resources (scrs) and multiple bridges. the scrs establish low-latency connectivity between master peripherals and slave peripherals. additionally, the scrs provide priority-based arbitration and facilitate concurrent data movement between master and slave peripherals. through an scr, the dsp subsystem can send data to the ddr2 memory controller without affecting a data transfer between the emac and l2 memory. bridges are mainly used to perform bus-width conversion as well as bus operating frequency conversion. for example, in figure 4-1 , bridge 6 performs a frequency conversion between a bus operating at dsp/3 clock rate and a bus operating at dsp/6 clock rate. furthermore, bridge 5 performs a bus-width conversion between a 64-bit bus and a 32-bit bus. the c64x+ megamodule, the edma3 transfer controllers (edma3tc[2:0]), and the various system peripherals can be classified into two categories: master peripherals and slave peripherals. master peripherals are typically capable of initiating read and write transfers in the system and do not rely on the edma3 or on the cpu to perform transfers to and from them. the system master peripherals include the c64x+ megamodule, the edma3 transfer controllers, emac, and vpss. not all master peripherals may connect to all slave peripherals. the supported connections are designated by "y" in table 4-1 . table 4-1. system connection matrix slave peripherals/modules master ddr2 scr2, scr6, peripherals/modules c64x+ sdma memory scr4 (1) scr7, scr8 (1) controller c64x+ mdma ? y ? y vpss ? y ? ? emac y y y y edma3tc's (edma3tc2/tc1/tc0) y y y y c64x+ cfg ? ? y y (1) all the peripherals/modules that support a connection to scr2, scr4, scr6, scr7, and scr8 have access to all peripherals/modules connected to those respective scrs. figure 4-1 displays the dm6431 system interconnect block diagram. the following is a list that helps in the interpretation of this diagram: the direction of the arrows indicates either a bus master or bus slave. the arrow originates at a bus master and terminates at a bus slave. the direction of the arrows does not indicate the direction of data flow. data flow is typically bi-directional for each of the documented bus paths. the pattern of each arrow's line indicates the clock rate at which it is operating? i.e., either dsp/3, dsp/6, or mxi/clkin clock rate. a peripheral may have multiple instances shown in figure 4-1 for the following reason: ? the peripheral/module has master port(s) for data transfers, as well as slave port(s) for register access, data access, and/or memory access. examples of these peripherals are c64x+ megamodule, edma3, vpss, and emac. system interconnect 114 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 4-1. system interconnect block diagram submit documentation feedback system interconnect 115 emac control module reg emac control module ram bridge 8 scr 3 scr 1 emac vpss edma3tc0 edma3tc1 scr 5 bridge 2 l2 cache edma3tc0 edma3tc1 read write 6464 64 64 32 32 edma3cc edma3tc2 bridge 5 64 bridge 4 64 bridge 3 64 32 scr 4 bridge 6 32 32 32 32 32 32 edma3tc2 scr 6 vpss reg emac reg mdio gpio system reg psc pllc1 pllc2 scr 2 uart0 hecc i2c pwm0 pwm1 pwm2 timer0 timer1 timer2 scr 7 emifa dsp/3 clock ratedsp/6 clock rate mxi/clkin clock rate 64x+ l2/l1 sdma ddr2 memory controller (memory/register) read write 6464 read write 64 64 64 64 64x+ mdma cfg 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 3232 32 32 32 32 32 32 32 64 dsp/6 clock rate dsp/3 clock rate dsp/6 clock rate mxi/clkin clock rate scr 8 mcbsp0 mcasp0 32 3232
5 device operating conditions 5.1 absolute maximum ratings over operating temperature range (unless otherwise tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com noted) (1) supply voltage ranges: core (cv dd ) (2) ?0.5 v to 1.5 v i/o, 3.3v (dv dd33 ) (2) ?0.5 v to 4.2 v i/o, 1.8v (dv ddr2 , ddr_vdddll, pll pwr18 , mxv dd ) (2) ?0.5 to 2.5 v input voltage ranges: v i i/o, 3.3-v pins ?0.5 v to 4.2 v v i i/o, 1.8 v ?0.5 v to 2.5 v output voltage ranges: v o i/o, 3.3-v pins ?0.5 v to 4.2 v v o i/o, 1.8 v ?0.5 v to 2.5 v operating junction temperature commercial 0c to 90c ranges, t j : automotive (q or s suffix) ?40c to 125c storage temperature range, t stg (default) ?65c to 150c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to v ss. device operating conditions 116 submit documentation feedback
5.2 recommended operating conditions tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 min nom max unit cv dd supply voltage, core (cv dd ) (1) (-3/-3q/-3s devices) 1.14 1.2 1.26 v supply voltage, i/o, 3.3v (dv dd33 ) 2.97 3.3 3.63 v dv dd supply voltage, i/o, 1.8v (dv ddr2 , ddr_vdddll, pll pwr18 , 1.71 1.8 1.89 v mxv dd (2) ) v ss supply ground (v ss , ddr_vssdll, mxv ss (3) ) 0 0 0 v ddr_vref ddr2 reference voltage (4) 0.49dv ddr2 0.5dv ddr2 0.51dv ddr2 v ddr_zp ddr2 impedance control, connected via 200 w resistor to v ss v ss v ddr_zn ddr2 impedance control, connected via 200 w resistor to dv ddr2 dv ddr2 v high-level input voltage, 3.3v (except i2c pins) 2 v v ih high-level input voltage, mxi/ clkin 0.65mxv v high-level input voltage, i2c 0.7dv dd33 low-level input voltage, 3.3v (except i2c pins) 0.8 v v il low-level input voltage, mxi/ clkin 0.35mxv (5) v low-level input voltage, i2c 0 0.3dv dd33 v commercial 0 90 c t j operating junction temperature (6) (7) automotive (q or s suffix) ?40 125 c commercial 0 70 c t a operating ambient temperature (7) automotive (q or s suffix) -40 85 c dsp operating frequency f sysclk1 (-3/-3q/-3s devices) 300 mhz (sysclk1) (1) future variants of ti soc devices may operate at voltages ranging from 0.9 v to 1.4 v to provide a range of system power/performance options. ti highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 v, 1.05 v, 1.1 v, 1.14 v, 1.2, 1.26 v with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of ti soc devices. (2) oscillator 1.8 v power supply (mxv dd ) can be connected to the same 1.8 v power supply as dv ddr2 . (3) oscillator ground (mxv ss ) must be kept separate from other grounds and connected directly to the crystal load capacitor ground. (4) ddr_vref is expected to equal 0.5dv ddr2 of the transmitting device and to track variations in the dv ddr2 . (5) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. (6) in the absence of a heat sink or direct thermal attachment on the top of the device, use the following formula to determine the device junction temperature: t j = t c + (power x psi jt ). power and t c can be measured by the user. section 7.1 , thermal data for zwt and section 7.1.1 , thermal data for zdu provide the junction-to-package top (psi jt ) value based on airflow in the system. in the presence of a heat sink or direct thermal attachment on the top of the device, additional calculations and considerations must be taken into account. for more detailed information on thermal considerations, measurements, and calculations, see the thermal considerations for tms320dm64xx, tms320dm64x, and tms320c6000 devices application report (literature number spraal9 ). (7) applications must meet both the operating junction temperature and operating ambient temperature requirements. for more detailed information on thermal considerations, measurements, and calculations, see the thermal considerations for tms320dm64xx, tms320dm64x, and tms320c6000 devices application report (literature number spraal9 ). submit documentation feedback device operating conditions 117
5.3 electrical characteristics over recommended ranges of supply voltage and operating tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com temperature (unless otherwise noted) parameter test conditions (1) min typ max unit high-level output voltage (3.3v i/o except v oh dv dd33 = min, i oh = max 2.4 v i2c pins) low-level output voltage (3.3v i/o except dv dd33 = min, i ol = max 0.4 v 2c pins) v ol low-level output voltage (3.3v i/o i2c pins) i o = 3 ma 0 0.4 v v i = v ss to dv dd33 with internal pullup 50 100 250 m a resistor (3) input current [dc] (except i2c capable pins) i i (2) v i = v ss to dv dd33 with internal pulldown ?250 ?100 ?50 m a resistor (3) input current [dc] (i2c) v i = v ss to dv dd33 10 m a clk_out0/pwm2/gpio[84] and gp[57] -8 ma i oh high-level output current [dc] ddr2 ?13.4 ma all other peripherals -4 ma clk_out0/pwm2/gpio[84] and gp[57] 8 ma i ol low-level output current [dc] ddr2 13.4 ma all other peripherals 4 ma v o = dv dd33 or v ss ; internal pull disabled 50 m a i oz (4) i/o off-state output current v o = dv dd33 or v ss ; internal pull enabled 100 m a cv dd = 1.2 v, dsp clock = 300 mhz 325 ma i cdd core (cv dd ) supply current (5) cv dd = 1.05 v, dsp clock = 300 mhz 278 ma i ddd 3.3v i/o (dv dd33 ) supply current (5) dv dd = 3.3 v, dsp clock = 300 mhz 13 ma dv dd = 1.8 v, cv dd = 1.2 v, dsp clock = 90 ma 300 mhz 1.8v i/o (dv ddr2 , ddr_vdddll, i ddd pllv prw18 , mxv dd ) supply current (5) dv dd = 1.8 v, cv dd = 1.05 v, dsp clock = 71 ma 300 mhz c i input capacitance 5 pf c o output capacitance 5 pf (1) for test conditions shown as min, max, or nom, use the appropriate value specified in the recommended operating conditions table. (2) i i applies to input-only pins and bi-directional pins. for input-only pins, i i indicates the input leakage current. for bi-directional pins, i i indicates the input leakage current and off-state (hi-z) output leakage current. (3) applies only to pins with an internal pullup (ipu) or pulldown (ipd) resistor. (4) i oz applies to output-only pins, indicating off-state (hi-z) output leakage current. (5) measured under the following conditions: 60% dsp cpu utilization doing typical activity (peripheral configurations, other housekeeping activities); ddr2 memory controller at 50% utilization (135 mhz), 50% writes, 32 bits, 50% bit switching; 2 mhz mcbsp0 at 100% utilization and 50% switching; timer0 at 100% utilization. at room temperature (25 c) for typical process zwt devices. the actual current draw varies across manufacturing processes and is highly application-dependent. for more details on core and i/o activity, as well as information relevant to board power supply design, see the tms320dm643x power consumption summary application report (literature number spraao6 ). 118 device operating conditions submit documentation feedback
6 peripheral information and electrical specifications 6.1 parameter information 6.1.1 3.3-v signal transition levels 6.1.2 3.3-v signal transition rates 6.1.3 timing parameters and board routing analysis tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 6-1. test load circuit for ac timing measurements the load capacitance value stated is only for characterization and measurement of ac timing signals. this load capacitance value does not indicate the maximum load the device is capable of driving. all input and output timing parameters are referenced to v ref for both "0" and "1" logic levels. for 3.3 v i/o, v ref = 1.5 v. for 1.8 v i/o, v ref = 0.9 v. figure 6-2. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks. figure 6-3. rise and fall transition time voltage reference levels all timings are tested with an input edge rate of 4 volts per nanosecond (4 v/ns). the timing parameter values specified in this data sheet do not include delays by board routings. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. submit documentation feedback peripheral information and electrical specifications 119 t ransmission line 4.0 pf 1.85 pf z0 = 50 w (see note) tester pin electronics data sheet t iming reference point outputunder test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmission line ef fects must be taken into account. a transmission line with a delay of 2 ns can be used to produce the desired transmission line ef fect. the transmission line is intended as a load only . it is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. input requirements in this data sheet are tested with an input slew rate of < 4 v olts per nanosecond (4 v/ns) at the device pin. 42 w 3.5 nh device pin(see note) v ref v ref = v il max (or v ol max) v ref = v ih min (or v oh min)
6.2 recommended clock and control signal transition behavior tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com ti recommends utilizing the available i/o buffer information specification (ibis) models to analyze the timing characteristics correctly. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839 ). if needed, external logic hardware such as buffers may be used to compensate any timing differences. for the ddr2 memory controller interface, it is not necessary to use the ibis models to analyze timing characteristics. ti provides a pcb routing rules solution that describes the routing rules to ensure the ddr2 memory controller interface timings are met. see the implementing ddr2 pcb layout on the tms320dm643x dmp dmsoc application report (literature number spraal6 ). all clocks and control signals must transition between v ih and v il (or between v il and v ih ) in a monotonic manner. 120 peripheral information and electrical specifications submit documentation feedback
6.3 power supplies 6.3.1 power-supply sequencing 6.3.2 power-supply design considerations 6.3.3 power-supply decoupling 6.3.4 dm6431 power and clock domains tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 for more information regarding ti's power management products and suggested devices to power ti dsps, visit www.ti.com/dsppower . the dm6431 includes one core supply (cv dd ), and two i/o supplies?dv dd33 and dv ddr2 . to ensure proper device operation, a specific power-up sequence must be followed. some ti power-supply devices include features that facilitate power sequencing?for example, auto-track and slow-start/enable features. for more information on ti power supplies and their features, visit www.ti.com/dsppower . here is a summary of the power sequencing requirements: the power ramp order must be dv dd33 before dv ddr2 , and dv ddr2 before cv dd ?meaning during power up, the voltage at the dv ddr2 rail should never exceed the voltage at the dv dd33 rail. similarly, the voltage at the cv dd rail should never exceed the voltage at the dv ddr2 rail. from the time that power ramp begins, all power supplies (dv dd33 , dv ddr2 , cv dd ) must be stable within 200 ms. the term "stable" means reaching the recommended operating condition (see section 5.2 , recommended operating conditions table). core and i/o supply voltage regulators should be located close to the dsp to minimize inductance and resistance in the power delivery path. additionally, when designing for high-performance applications utilizing the dm6431 device, the pc board should include separate power planes for core, i/o, and ground; all bypassed with high-quality low-esl/esr capacitors. in order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the dsp. these caps need to be close to the dsp, no more than 1.25 cm maximum distance to be effective. physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. larger caps for each supply can be placed further away for bulk decoupling. large bulk caps (on the order of 100 m f) should be furthest away, but still as close as possible. large caps for each supply should be placed outside of the bga footprint. as with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered. for more details on capacitor usage and placement, see the implementing ddr2 pcb layout on the tms320dm643x dmp dmsoc application report (literature number spraal6 ). the dm6431 includes one single power domain ? the "always on" power domain. the "always on" power domain is always on when the chip is on. the "always on" domain is powered by the cv dd pins of the dm6431. all dm6431 modules lie within the "always on" power domain. table 6-1 provides a listing of the dm6431 clock domains. one primary reference clock is required for the dm6431 device. it can be either a crystal input or driven by external oscillators. a 27-mhz crystal is recommended for the plls, which generate the internal clocks for the digital media processor (dmp), peripherals, and edma3. the dm6431 architecture is divided into the power and clock domains shown in table 6-1 . table 6-2 and table 6-3 further discuss the clock domains and their ratios. figure 6-4 shows the clock domain block diagram. submit documentation feedback peripheral information and electrical specifications 121
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-1. dm6431 power and clock domains power domain clock domain peripheral/module always on clkin uart0 always on clkin hecc always on clkin i2c always on clkin timer0 always on clkin timer1 always on clkin timer2 always on clkin pwm0 always on clkin pwm1 always on clkin pwm2 always on clkdiv3 ddr2 always on clkdiv3 vpss always on clkdiv3 edma always on clkdiv3 scr always on clkdiv6 gpsc always on clkdiv6 lpscs always on clkdiv6 pllc1 always on clkdiv6 pllc2 always on clkdiv6 ice pick always on clkdiv6 emifa always on clkdiv6 emac always on clkdiv6 mcasp0 always on clkdiv6 mcbsp0 always on clkdiv6 gpio always on clkdiv1 c64x+ cpu table 6-2. dm6431 clock domains domain clock fixed ratio vs. example subsystem clock domain source sysclk1 frequency frequency (mhz) peripherals (clkin domain) clkin pllc1 auxclk (1) ? 27 mhz dsp subsystem clkdiv1 pllc1 sysclk1 1:1 594 mhz edma3 clkdiv3 pllc1 sysclk2 1:3 198 mhz vpss clkdiv3 pllc1 sysclk2 1:3 198 mhz peripherals (clkdiv3 domain) clkdiv3 pllc1 sysclk2 1:3 198 mhz peripherals (clkdiv6 domain) clkdiv6 pllc1 sysclk3 1:6 99 mhz (1) pllc1 auxclk runs at exactly the same frequency as the device clock source from the mxi/clkin pin. the clkdiv1:clkdiv3:clkdiv6 ratio must be strictly followed by programming the pll controller 1 (pllc1) plldiv1, plldiv2, and plldiv3 registers appropriately (see table 6-3 ). table 6-3. pllc1 programming for clkdiv1, clkdiv3, clkdiv6 domains clkdiv1 domain clkdiv3 domain clkdiv6 domain (sysclk1) (sysclk2) (sysclk3) pll1 pll1 pll1 plldiv1.ratio plldiv2.ratio plldiv3.ratio divide-down divide-down divide-down div1 /1 0 /3 2 /6 5 div2 /2 1 /6 5 /12 11 div3 /3 2 /9 8 /18 17 peripheral information and electrical specifications 122 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 6-4. pll1 and pll2 clock domain block diagram for further detail on pll1 and pll2, see the structure block diagrams figure 6-5 and figure 6-6 , respectively. figure 6-5. pll1 structure block diagram submit documentation feedback peripheral information and electrical specifications 123 dsp subsystem sysclk1 sysclk3 scr edma ddr2 phyddr2 vtp ddr2 mem ctlr plldiv1 (/2) bpdiv pll controller 2 pll controller 1 plldiv2 (/3) plldiv3 (/6) plldiv1 (/1) sysclk2 uart0 i2c t imers (x3) pwms (x3) emac emifa mcasp0 mcbsp0 gpio mxi/clkin (27 mhz) oscdiv1 (/1) hecc obsclk(clkout0 pin) auxclk plldiv1 (/1) plldiv3 (/6) plldiv2 (/3) sysclk1(clkdiv1 domain) sysclk3(clkdiv6 domain) sysclk2(clkdiv3 domain) 10 pllm pll 0 1 clkmode clkin oscin pllen auxclk(clkin domain) oscdiv1 obsclk(clkout0 pin) pllout
6.3.5 power and sleep controller (psc) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 6-6. pll2 structure block diagram the power and sleep controller (psc) controls power by turning off unused power domains or by gating off clocks to individual peripherals/modules. the dm6431 device only utilizes the clock gating feature of the psc for power savings. the psc consists of a global psc (gpsc) and a set of local pscs (lpscs). the gpsc contains memory mapped registers, psc interrupt control, and a state machine for each peripheral/module. an lpsc is associated with each peripheral/module and provides clock and reset control. the lpscs for dm6431 are shown in table 6-4 . the psc register memory map is given in table 6-5 . for more details on the psc, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). peripheral information and electrical specifications 124 submit documentation feedback plldiv1 (/2) 10 pllm pll 0 1 bpdiv clkmode clkin oscin pllen pll2_sysclk1(ddr2 phy) pll2_sysclkbp (ddr2 vtp) pllout
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-4. dm6431 lpsc assignments lpsc peripheral/module lpsc peripheral/module lpsc peripheral/module number number number 0 vpss dma 14 emifa 28 timer1 1 vpss mmr 15 reserved 29 reserved 2 edmacc 16 mcbsp0 30 reserved 3 edmatc0 17 reserved 31 reserved 4 edmatc1 18 i2c 32 reserved 5 edmatc2 19 uart0 33 reserved 6 emac memory controller 20 reserved 34 reserved 7 mdio 21 reserved 35 reserved 8 emac 22 hecc 36 reserved 9 mcasp0 23 pwm0 37 reserved 10 reserved 24 pwm1 38 reserved 11 reserved 25 pwm2 39 c64x+ cpu 12 reserved 26 gpio 40 reserved 13 ddr2 memory controller 27 timer0 table 6-5. psc register memory map register hex address range description acronym 0x01c4 1000 pid peripheral revision and class information register 0x01c4 1004 - 0x01c4 100f ? reserved 0x01c4 1010 ? reserved 0x01c4 1014 ? reserved 0x01c4 1018 inteval interrupt evaluation register 0x01c4 101c - 0x01c4 103f ? reserved 0x01c4 1040 ? reserved 0x01c4 1044 merrpr1 module error pending 1 (mod 32- 63) register 0x01c4 1048 - 0x01c4 104f ? reserved 0x01c4 1050 ? reserved 0x01c4 1054 merrcr1 module error clear 1 (mod 32 - 63) register 0x01c4 1058 - 0x01c4 105f ? reserved 0x01c4 1060 ? reserved 0x01c4 1064 - 0x01c4 1067 ? reserved 0x01c4 1068 ? reserved 0x01c4 106c - 0x01c4 111f ? reserved 0x01c4 1120 ptcmd power domain transition command register 0x01c4 1124 - 0x01c4 1127 ? reserved 0x01c4 1128 ptstat power domain transition status register 0x01c4 112c - 0x01c4 11ff ? reserved 0x01c4 1200 pdstat0 power domain status 0 register (always on) 0x01c4 1204 - 0x01c4 12ff ? reserved 0x01c4 1300 pdctl0 power domain control 0 register (always on) 0x01c4 1304 - 0x1c4 150f ? reserved 0x01c4 1510 ? reserved 0x01c4 1514 ? reserved 0x01c4 1518 - 0x01c4 15ff ? reserved 0x01c4 1600 - 0x01c4 17ff ? reserved submit documentation feedback peripheral information and electrical specifications 125
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-5. psc register memory map (continued) register hex address range description acronym 0x01c4 1800 mdstat0 module status 0 register (vpss dma) 0x01c4 1804 mdstat1 module status 1 register (vpss mmr) 0x01c4 1808 mdstat2 module status 2 register (edmacc) 0x01c4 180c mdstat3 module status 3 register (edmatc0) 0x01c4 1810 mdstat4 module status 4 register (edmatc1) 0x01c4 1814 mdstat5 module status 5 register (edmatc2) 0x01c4 1818 mdstat6 module status 6 register (emac memory controller) 0x01c4 181c mdstat7 module status 7 register (mdio) 0x01c4 1820 mdstat8 module status 8 register (emac) 0x01c4 1824 mdstat9 module status 9 register (mcasp0) 0x01c4 1828 ? reserved 0x01c4 182c ? reserved 0x01c4 1830 ? reserved 0x01c4 1834 mdstat13 module status 13 register (ddr2) 0x01c4 1838 mdstat14 module status 14 register (emifa) 0x01c4 183c ? reserved 0x01c4 1840 mdstat16 module status 16 register (mcbsp0) 0x01c4 1844 ? reserved 0x01c4 1848 mdstat18 module status 18 register (i2c) 0x01c4 184c mdstat19 module status 19 register (uart0) 0x01c4 1850 ? reserved 0x01c4 1854 ? reserved 0x01c4 1858 mdstat22 module status 22 register (hecc) 0x01c4 185c mdstat23 module status 23 register (pwm0) 0x01c4 1860 mdstat24 module status 24 register (pwm1) 0x01c4 1864 mdstat25 module status 25 register (pwm2) 0x01c4 1868 mdstat26 module status 26 register (gpio) 0x01c4 186c mdstat27 module status 27 register (timer0) 0x01c4 1870 mdstat28 module status 28 register (timer1) 0x01c4 1874 - 0x01c4 189b ? reserved 0x01c4 189c mdstat39 module status 39 register (c64x+ cpu) 0x01c4 18a0 ? reserved 0x01c4 18a4 - 0x01c4 19ff ? reserved 0x01c4 1a00 mdctl0 module control 0 register (vpss dma) 0x01c4 1a04 mdctl1 module control 1 register (vpss mmr) 0x01c4 1a08 mdctl2 module control 2 register (edmacc) 0x01c4 1a0c mdctl3 module control 3 register (edmatc0) 0x01c4 1a10 mdctl4 module control 4 register (edmatc1) 0x01c4 1a14 mdctl5 module control 5 register (edmatc2) 0x01c4 1a18 mdctl6 module control 6 register (emac memory controller) 0x01c4 1a1c mdctl7 module control 7 register (mdio) 0x01c4 1a20 mdctl8 module control 8 register (emac) 0x01c4 1a24 mdctl9 module control 9 register (mcasp0) 0x01c4 1a28 ? reserved 0x01c4 1a2c ? reserved 0x01c4 1a30 ? reserved peripheral information and electrical specifications 126 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-5. psc register memory map (continued) register hex address range description acronym 0x01c4 1a34 mdctl13 module control 13 register (ddr2) 0x01c4 1a38 mdctl14 module control 14 register (emifa) 0x01c4 1a3c ? reserved 0x01c4 1a40 mdctl16 module control 16 register (mcbsp0) 0x01c4 1a44 ? reserved 0x01c4 1a48 mdctl18 module control 18 register (i2c) 0x01c4 1a4c mdctl19 module control 19 register (uart0) 0x01c4 1a50 ? reserved 0x01c4 1a54 ? reserved 0x01c4 1a58 mdctl22 module control 22 register (hecc) 0x01c4 1a5c mdctl23 module control 23 register (pwm0) 0x01c4 1a60 mdctl24 module control 24 register (pwm1) 0x01c4 1a64 mdctl25 module control 25 register (pwm2) 0x01c4 1a68 mdctl26 module control 26 register (gpio) 0x01c4 1a6c mdctl27 module control 27 register (timer0) 0x01c4 1a70 mdctl28 module control 28 register (timer1) 0x01c4 1a74 - 0x01c4 1a9b ? reserved 0x01c4 1a9c mdctl39 module control 39 register (c64x+ cpu) 0x01c4 1aa0 ? reserved 0x01c4 1aa4 - 0x01c4 1fff ? reserved submit documentation feedback peripheral information and electrical specifications 127
6.4 enhanced direct memory access (edma3) controller 6.4.1 edma3 channel synchronization events tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the edma controller handles all data transfers between memories and the device slave peripherals on the dm6431 device. these data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses. these are summarized as follows: transfer to/from on-chip memories ? dsp l1d memory ? dsp l2 memory transfer to/from external storage ? ddr2 sdram ? nand flash ? asynchronous emif (emifa) transfer to/from peripherals/hosts ? mcbsp0 ? mcasp0 ? pwm ? uart0 ? hecc the edma supports two addressing modes: constant addressing and increment addressing. on the dm6431, constant addressing mode is not supported by any peripheral or internal memory. for more information on these two addressing modes, see the tms320dm643x dmp enhanced direct memory access (edma3) controller user?s guide (literature number spru987 ). the edma supports up to 64 edma channels which service peripheral devices and external memory. table 6-6 lists the source of edma synchronization events associated with each of the programmable edma channels. for the dm6431 device, the association of an event to a channel is fixed; each of the edma channels has one specific event associated with it. these specific events are captured in the edma event registers (er, erh) even if the events are disabled by the edma event enable registers (eer, eerh). for more detailed information on the edma module and how edma events are enabled, captured, processed, linked, chained, and cleared, etc., see the tms320dm643x dmp enhanced direct memory access (edma3) controller user?s guide (literature number spru987 ). table 6-6. dm6431 edma channel synchronization events (1) edma event name event description channel 0-1 ? reserved 2 xevt0 mcbsp0 transmit event 3 revt0 mcbsp0 receive event 4 ? reserved 5 ? reserved 6 ? reserved 7 ? reserved 8 ? reserved 9 ? reserved 10 axevte0 mcasp0 transmit event even 11 axevto0 mcasp0 transmit event odd 12 axevt0 mcasp0 transmit event (1) in addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. for more detailed information on edma event-transfer chaining, see the document support section for the enhanced direct memory access (edma) controller reference guide. peripheral information and electrical specifications 128 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-6. dm6431 edma channel synchronization events (continued) edma event name event description channel 13 arevte0 mcasp0 receive event even 14 arevto0 mcasp0 receive event odd 15 arevt0 mcasp0 receive event 16-21 ? reserved 22 urxevt0 uart 0 receive event 23 utxevt0 uart 0 transmit event 24 ? reserved 25 ? reserved 26 ? reserved 27 ? reserved 28 icrevt i2c receive event 29 icxevt i2c transmit event 30-31 ? reserved 32 gpint0 gpio 0 interrupt 33 gpint1 gpio 1 interrupt 34 gpint2 gpio 2 interrupt 35 gpint3 gpio 3 interrupt 36 gpint4 gpio 4 interrupt 37 gpint5 gpio 5 interrupt 38 gpint6 gpio 6 interrupt 39 gpint7 gpio 7 interrupt 40 gpbnkint0 gpio bank 0 interrupt 41 gpbnkint1 gpio bank 1 interrupt 42 gpbnkint2 gpio bank 2 interrupt 43 gpbnkint3 gpio bank 3 interrupt 44 gpbnkint4 gpio bank 4 interrupt 45 gpbnkint5 gpio bank 5 interrupt 46 gpbnkint6 gpio bank 6 interrupt 47 ? reserved 48 tevtl0 timer 0 event low interrupt 49 tevth0 timer 0 event high interrupt 50 tevtl1 timer 1 event low interrupt 51 tevth1 timer 1 evemt high interrupt 52 pwm0 pwm 0 event 53 pwm1 pwm 1 event 54 pwm2 pwm 2 event 55-63 ? reserved submit documentation feedback peripheral information and electrical specifications 129
6.4.2 edma peripheral register description(s) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-7 lists the edma registers, their corresponding acronyms, and dm6431 device memory locations. table 6-7. dm6431 edma registers hex address acronym register name channel controller registers 0x01c0 0000 - 0x01c0 0003 reserved 0x01c0 0004 cccfg edma3cc configuration register 0x01c0 0008 - 0x01c0 01ff reserved global registers 0x01c0 0200 qchmap0 qdma channel 0 mapping to param register 0x01c0 0204 qchmap1 qdma channel 1 mapping to param register 0x01c0 0208 qchmap2 qdma channel 2 mapping to param register 0x01c0 020c qchmap3 qdma channel 3 mapping to param register 0x01c0 0210 qchmap4 qdma channel 4 mapping to param register 0x01c0 0214 qchmap5 qdma channel 5 mapping to param register 0x01c0 0218 qchmap6 qdma channel 6 mapping to param register 0x01c0 021c qchmap7 qdma channel 7 mapping to param register 0x01c0 0240 dmaqnum0 dma queue number register 0 (channels 00 to 07) 0x01c0 0244 dmaqnum1 dma queue number register 1 (channels 08 to 15) 0x01c0 0248 dmaqnum2 dma queue number register 2 (channels 16 to 23) 0x01c0 024c dmaqnum3 dma queue number register 3 (channels 24 to 31) 0x01c0 0250 dmaqnum4 dma queue number register 4 (channels 32 to 39) 0x01c0 0254 dmaqnum5 dma queue number register 5 (channels 40 to 47) 0x01c0 0258 dmaqnum6 dma queue number register 6 (channels 48 to 55) 0x01c0 025c dmaqnum7 dma queue number register 7 (channels 56 to 63) 0x01c0 0260 qdmaqnum cc qdma queue number 0x01c0 0264 - 0x01c0 0283 ? reserved 0x01c0 0284 quepri queue priority register 0x01c0 0288 - 0x01c0 02ff ? reserved 0x01c0 0300 emr event missed register 0x01c0 0304 emrh event missed register high 0x01c0 0308 emcr event missed clear register 0x01c0 030c emcrh event missed clear register high 0x01c0 0310 qemr qdma event missed register 0x01c0 0314 qemcr qdma event missed clear register 0x01c0 0318 ccerr edma3cc error register 0x01c0 031c ccerrclr edma3cc error clear register 0x01c0 0320 eeval error evaluate register 0x01c0 0340 drae0 dma region access enable register for region 0 0x01c0 0344 draeh0 dma region access enable register high for region 0 0x01c0 0348 drae1 dma region access enable register for region 1 0x01c0 034c draeh1 dma region access enable register high for region 1 0x01c0 0350 ? reserved 0x01c0 0354 ? reserved 0x01c0 0358 ? reserved 0x01c0 035c ? reserved 0x01c0 0360 - 0x01c0 037c ? reserved 0x01c0 0380 qrae0 qdma region access enable register for region 0 peripheral information and electrical specifications 130 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-7. dm6431 edma registers (continued) hex address acronym register name 0x01c0 0384 qrae1 qdma region access enable register for region 1 0x01c0 0388 ? reserved 0x01c0 038c ? reserved 0x01c0 0390 - 0x01c0 039c ? reserved 0x01c0 0400 q0e0 event q0 entry 0 register 0x01c0 0404 q0e1 event q0 entry 1 register 0x01c0 0408 q0e2 event q0 entry 2 register 0x01c0 040c q0e3 event q0 entry 3 register 0x01c0 0410 q0e4 event q0 entry 4 register 0x01c0 0414 q0e5 event q0 entry 5 register 0x01c0 0418 q0e6 event q0 entry 6 register 0x01c0 041c q0e7 event q0 entry 7 register 0x01c0 0420 q0e8 event q0 entry 8 register 0x01c0 0424 q0e9 event q0 entry 9 register 0x01c0 0428 q0e10 event q0 entry 10 register 0x01c0 042c q0e11 event q0 entry 11 register 0x01c0 0430 q0e12 event q0 entry 12 register 0x01c0 0434 q0e13 event q0 entry 13 register 0x01c0 0438 q0e14 event q0 entry 14 register 0x01c0 043c q0e15 event q0 entry 15 register 0x01c0 0440 q1e0 event q1 entry 0 register 0x01c0 0444 q1e1 event q1 entry 1 register 0x01c0 0448 q1e2 event q1 entry 2 register 0x01c0 044c q1e3 event q1 entry 3 register 0x01c0 0450 q1e4 event q1 entry 4 register 0x01c0 0454 q1e5 event q1 entry 5 register 0x01c0 0458 q1e6 event q1 entry 6 register 0x01c0 045c q1e7 event q1 entry 7 register 0x01c0 0460 q1e8 event q1 entry 8 register 0x01c0 0464 q1e9 event q1 entry 9 register 0x01c0 0468 q1e10 event q1 entry 10 register 0x01c0 046c q1e11 event q1 entry 11 register 0x01c0 0470 q1e12 event q1 entry 12 register 0x01c0 0474 q1e13 event q1 entry 13 register 0x01c0 0478 q1e14 event q1 entry 14 register 0x01c0 047c q1e15 event q1 entry 15 register 0x01c0 0480 q2e0 event q2 entry 0 register 0x01c0 0484 q2e1 event q2 entry 1 register 0x01c0 0488 q2e2 event q2 entry 2 register 0x01c0 048c q2e3 event q2 entry 3 register 0x01c0 0490 q2e4 event q2 entry 4 register 0x01c0 0494 q2e5 event q2 entry 5 register 0x01c0 0498 q2e6 event q2 entry 6 register 0x01c0 049c q2e7 event q2 entry 7 register 0x01c0 04a0 q2e8 event q2 entry 8 register 0x01c0 04a4 q2e9 event q2 entry 9 register 0x01c0 04a8 q2e10 event q2 entry 10 register submit documentation feedback peripheral information and electrical specifications 131
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-7. dm6431 edma registers (continued) hex address acronym register name 0x01c0 04ac q2e11 event q2 entry 11 register 0x01c0 04b0 q2e12 event q2 entry 12 register 0x01c0 04b4 q2e13 event q2 entry 13 register 0x01c0 04b8 q2e14 event q2 entry 14 register 0x01c0 04bc q2e15 event q2 entry 15 register 0x01c0 04c0 - 0x01c0 05ff reserved 0x01c0 0600 qstat0 queue 0 status register 0x01c0 0604 qstat1 queue 1 status register 0x01c0 0608 qstat2 queue 2 status register 0x01c0 060c - 0x01c0 061f reserved 0x01c0 0620 qwmthra queue watermark threshold a register for q[2:0] 0x01c0 0624 ? reserved 0x01c0 0640 ccstat edma3cc status register 0x01c0 0644 - 0x01c0 0fff reserved global channel registers 0x01c0 1000 er event register 0x01c0 1004 erh event register high 0x01c0 1008 ecr event clear register 0x01c0 100c ecrh event clear register high 0x01c0 1010 esr event set register 0x01c0 1014 esrh event set register high 0x01c0 1018 cer chained event register 0x01c0 101c cerh chained event register high 0x01c0 1020 eer event enable register 0x01c0 1024 eerh event enable register high 0x01c0 1028 eecr event enable clear register 0x01c0 102c eecrh event enable clear register high 0x01c0 1030 eesr event enable set register 0x01c0 1034 eesrh event enable set register high 0x01c0 1038 ser secondary event register 0x01c0 103c serh secondary event register high 0x01c0 1040 secr secondary event clear register 0x01c0 1044 secrh secondary event clear register high 0x01c0 1048 - 0x01c0 104f reserved 0x01c0 1050 ier interrupt enable register 0x01c0 1054 ierh interrupt enable register high 0x01c0 1058 iecr interrupt enable clear register 0x01c0 105c iecrh interrupt enable clear register high 0x01c0 1060 iesr interrupt enable set register 0x01c0 1064 iesrh interrupt enable set register high 0x01c0 1068 ipr interrupt pending register 0x01c0 106c iprh interrupt pending register high 0x01c0 1070 icr interrupt clear register 0x01c0 1074 icrh interrupt clear register high 0x01c0 1078 ieval interrupt evaluate register 0x01c0 1080 qer qdma event register 0x01c0 1084 qeer qdma event enable register peripheral information and electrical specifications 132 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-7. dm6431 edma registers (continued) hex address acronym register name 0x01c0 1088 qeecr qdma event enable clear register 0x01c0 108c qeesr qdma event enable set register 0x01c0 1090 qser qdma secondary event register 0x01c0 1094 qsecr qdma secondary event clear register 0x01c0 1098 - 0x01c0 1fff reserved shadow region 0 channel registers 0x01c0 2000 er event register 0x01c0 2004 erh event register high 0x01c0 2008 ecr event clear register 0x01c0 200c ecrh event clear register high 0x01c0 2010 esr event set register 0x01c0 2014 esrh event set register high 0x01c0 2018 cer chained event register 0x01c0 201c cerh chained event register high 0x01c0 2020 eer event enable register 0x01c0 2024 eerh event enable register high 0x01c0 2028 eecr event enable clear register 0x01c0 202c eecrh event enable clear register high 0x01c0 2030 eesr event enable set register 0x01c0 2034 eesrh event enable set register high 0x01c0 2038 ser secondary event register 0x01c0 203c serh secondary event register high 0x01c0 2040 secr secondary event clear register 0x01c0 2044 secrh secondary event clear register high 0x01c0 2048 - 0x01c0 204c - reserved 0x01c0 2050 ier interrupt enable register 0x01c0 2054 ierh interrupt enable register high 0x01c0 2058 iecr interrupt enable clear register 0x01c0 205c iecrh interrupt enable clear register high 0x01c0 2060 iesr interrupt enable set register 0x01c0 2064 iesrh interrupt enable set register high 0x01c0 2068 ipr interrupt pending register 0x01c0 206c iprh interrupt pending register high 0x01c0 2070 icr interrupt clear register 0x01c0 2074 icrh interrupt clear register high 0x01c0 2078 ieval interrupt evaluate register 0x01c0 207c - reserved 0x01c0 2080 qer qdma event register 0x01c0 2084 qeer qdma event enable register 0x01c0 2088 qeecr qdma event enable clear register 0x01c0 208c qeesr qdma event enable set register 0x01c0 2090 qser qdma secondary event register 0x01c0 2094 qsecr qdma secondary event clear register 0x01c0 2098 - 0x01c0 21fc - reserved shadow region 1 channel registers 0x01c0 2200 er event register 0x01c0 2204 erh event register high submit documentation feedback peripheral information and electrical specifications 133
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-7. dm6431 edma registers (continued) hex address acronym register name 0x01c0 2208 ecr event clear register 0x01c0 220c ecrh event clear register high 0x01c0 2210 esr event set register 0x01c0 2214 esrh event set register high 0x01c0 2218 cer chained event register 0x01c0 221c cerh chained event register high 0x01c0 2220 eer event enable register 0x01c0 2224 eerh event enable register high 0x01c0 2228 eecr event enable clear register 0x01c0 222c eecrh event enable clear register high 0x01c0 2230 eesr event enable set register 0x01c0 2234 eesrh event enable set register high 0x01c0 2238 ser secondary event register 0x01c0 223c serh secondary event register high 0x01c0 2240 secr secondary event clear register 0x01c0 2244 secrh secondary event clear register high 0x01c0 2248 - 0x01c0 224c - reserved 0x01c0 2250 ier interrupt enable register 0x01c0 2254 ierh interrupt enable register high 0x01c0 2258 iecr interrupt enable clear register 0x01c0 225c iecrh interrupt enable clear register high 0x01c0 2260 iesr interrupt enable set register 0x01c0 2264 iesrh interrupt enable set register high 0x01c0 2268 ipr interrupt pending register 0x01c0 226c iprh interrupt pending register high 0x01c0 2270 icr interrupt clear register 0x01c0 2274 icrh interrupt clear register high 0x01c0 2278 ieval interrupt evaluate register 0x01c0 227c - reserved 0x01c0 2280 qer qdma event register 0x01c0 2284 qeer qdma event enable register 0x01c0 2288 qeecr qdma event enable clear register 0x01c0 228c qeesr qdma event enable set register 0x01c0 2290 qser qdma secondary event register 0x01c0 2294 qsecr qdma secondary event clear register 0x01c0 2298 - 0x01c0 23fc - reserved 0x01c0 2400 - 0x01c0 25fc - reserved 0x01c0 2600 - 0x01c0 27fc - reserved 0x01c0 2800 - 0x01c0 29fc - reserved 0x01c0 2a00 - 0x01c0 2bfc - reserved 0x01c0 2c00 - 0x01c0 2dfc - reserved 0x01c0 2e00 - 0x01c0 2ffc - reserved 0x01c0 2ffd - 0x01c0 3fff - reserved 0x01c0 4000 - 0x01c0 4fff - parameter set ram (see table 6-8 ) 0x01c0 5000 - 0x01c0 7fff - reserved 0x01c0 8000 - 0x01c0 ffff - reserved transfer controller 0 registers peripheral information and electrical specifications 134 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-7. dm6431 edma registers (continued) hex address acronym register name 0x01c1 0000 - reserved 0x01c1 0004 tccfg edma3 tc0 configuration register 0x01c1 0008 - 0x01c1 00ff - reserved 0x01c1 0100 tcstat edma3 tc0 channel status register 0x01c1 0104 - 0x01c1 0110 - reserved 0x01c1 0114 - 0x01c1 011f - reserved 0x01c1 0120 errstat edma3 tc0 error status register 0x01c1 0124 erren edma3 tc0 error enable register 0x01c1 0128 errclr edma3 tc0 error clear register 0x01c1 012c errdet edma3 tc0 error details register 0x01c1 0130 errcmd edma3 tc0 error interrupt command register 0x01c1 0134 - 0x01c1 013f - reserved 0x01c1 0140 rdrate edma3 tc0 read command rate register 0x01c1 0144 - 0x01c1 01ff - reserved 0x01c1 0200 - 0x01c1 023f - reserved 0x01c1 0240 saopt edma3 tc0 source active options register 0x01c1 0244 sasrc edma3 tc0 source active source address register 0x01c1 0248 sacnt edma3 tc0 source active count register 0x01c1 024c sadst edma3 tc0 source active destination address register 0x01c1 0250 sabidx edma3 tc0 active b-index register 0x01c1 0254 sampprxy edma3 tc0 source active memory protection proxy register 0x01c1 0258 sacntrld edma3 tc0 source active count reload register 0x01c1 025c sasrcbref edma3 tc0 source active source address b-reference register 0x01c1 0260 sadstbref edma3 tc0 source active destination address b-reference register 0x01c1 0264 - 0x01c1 027f - reserved 0x01c1 0280 dfcntrld edma3 tc0 destination fifo set count reload register 0x01c1 0284 dfsrcbref edma3 tc0 destination fifo set source address b-reference register edma3 tc0 destination fifo set destination address b-reference 0x01c1 0288 dfdstbref register 0x01c1 028c - 0x01c1 02ff - reserved 0x01c1 0300 dfopt0 edma3 tc0 destination fifo options register 0 0x01c1 0304 dfsrc0 edma3 tc0 destination fifo source address register 0 0x01c1 0308 dfcnt0 edma3 tc0 destination fifo count register 0 0x01c1 030c dfdst0 edma3 tc0 destination fifo destination address register 0 0x01c1 0310 dfbidx0 edma3 tc0 destination fifo b-index register 0 0x01c1 0314 dfmpprxy0 edma3 tc0 destination fifo memory protection proxy register 0 0x01c1 0318 - 0x01c1 033f - reserved 0x01c1 0340 dfopt1 edma3 tc0 destination fifo options register 1 0x01c1 0344 dfsrc1 edma3 tc0 destination fifo source address register 1 0x01c1 0348 dfcnt1 edma3 tc0 destination fifo count register 1 0x01c1 034c dfdst1 edma3 tc0 destination fifo destination address register 1 0x01c1 0350 dfbidx1 edma3 tc0 destination fifo b-index register 1 0x01c1 0354 dfmpprxy1 edma3 tc0 destination fifo memory protection proxy register 1 0x01c1 0358 - 0x01c1 037f - reserved 0x01c1 0380 dfopt2 edma3 tc0 destination fifo options register 2 0x01c1 0384 dfsrc2 edma3 tc0 destination fifo source address register 2 0x01c1 0388 dfcnt2 edma3 tc0 destination fifo count register 2 submit documentation feedback peripheral information and electrical specifications 135
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-7. dm6431 edma registers (continued) hex address acronym register name 0x01c1 038c dfdst2 edma3 tc0 destination fifo destination address register 2 0x01c1 0390 dfbidx2 edma3 tc0 destination fifo b-index register 2 0x01c1 0394 dfmpprxy2 edma3 tc0 destination fifo memory protection proxy register 2 0x01c1 0398 - 0x01c1 03bf - reserved 0x01c1 03c0 dfopt3 edma3 tc0 destination fifo options register 3 0x01c1 03c4 dfsrc3 edma3 tc0 destination fifo source address register 3 0x01c1 03c8 dfcnt3 edma3 tc0 destination fifo count register 3 0x01c1 03cc dfdst3 edma3 tc0 destination fifo destination address register 3 0x01c1 03d0 dfbidx3 edma3 tc0 destination fifo b-index register 3 0x01c1 03d4 dfmpprxy3 edma3 tc0 destination fifo memory protection proxy register 3 0x01c1 03d8 - 0x01c1 03ff - reserved transfer controller 1 registers 0x01c1 0400 - reserved 0x01c1 0404 tccfg edma3 tc1 configuration register 0x01c1 0408 - 0x01c1 04ff - reserved 0x01c1 0500 tcstat edma3 tc1 channel status register 0x01c1 0504 - 0x01c1 0510 - reserved 0x01c1 0514 - 0x01c1 051f - reserved 0x01c1 0520 errstat edma3 tc1 error status register 0x01c1 0524 erren edma3 tc1 error enable register 0x01c1 0528 errclr edma3 tc1 error clear register 0x01c1 052c errdet edma3 tc1 error details register 0x01c1 0530 errcmd edma3 tc1 error interrupt command register 0x01c1 0534 - 0x01c1 053f - reserved 0x01c1 0540 rdrate edma3 tc1 read command rate register 0x01c1 0544 - 0x01c1 05ff - reserved 0x01c1 0600 - 0x01c1 063f - reserved 0x01c1 0640 saopt edma3 tc1 source active options register 0x01c1 0644 sasrc edma3 tc1 source active source address register 0x01c1 0648 sacnt edma3 tc1 source active count register 0x01c1 064c sadst edma3 tc1 source active destination address register 0x01c1 0650 sabidx edma3 tc1 active b-index register 0x01c1 0654 sampprxy edma3 tc1 source active memory protection proxy register 0x01c1 0658 sacntrld edma3 tc1 source active count reload register 0x01c1 065c sasrcbref edma3 tc1 source active source address b-reference register 0x01c1 0660 sadstbref edma3 tc1 source active destination address b-reference register 0x01c1 0664 - 0x01c1 067f - reserved 0x01c1 0680 dfcntrld edma3 tc1 destination fifo set count reload register 0x01c1 0684 dfsrcbref edma3 tc1 destination fifo set source address b-reference register edma3 tc1 destination fifo set destination address b-reference 0x01c1 0688 dfdstbref register 0x01c1 068c - 0x01c1 06ff - reserved 0x01c1 0700 dfopt0 edma3 tc1 destination fifo options register 0 0x01c1 0704 dfsrc0 edma3 tc1 destination fifo source address register 0 0x01c1 0708 dfcnt0 edma3 tc1 destination fifo count register 0 0x01c1 070c dfdst0 edma3 tc1 destination fifo destination address register 0 0x01c1 0710 dfbidx0 edma3 tc1 destination fifo b-index register 0 peripheral information and electrical specifications 136 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-7. dm6431 edma registers (continued) hex address acronym register name 0x01c1 0714 dfmpprxy0 edma3 tc1 destination fifo memory protection proxy register 0 0x01c1 0718 - 0x01c1 073f - reserved 0x01c1 0740 dfopt1 edma3 tc1 destination fifo options register 1 0x01c1 0744 dfsrc1 edma3 tc1 destination fifo source address register 1 0x01c1 0748 dfcnt1 edma3 tc1 destination fifo count register 1 0x01c1 074c dfdst1 edma3 tc1 destination fifo destination address register 1 0x01c1 0750 dfbidx1 edma3 tc1 destination fifo b-index register 1 0x01c1 0754 dfmpprxy1 edma3 tc1 destination fifo memory protection proxy register 1 0x01c1 0758 - 0x01c1 077f - reserved 0x01c1 0780 dfopt2 edma3 tc1 destination fifo options register 2 0x01c1 0784 dfsrc2 edma3 tc1 destination fifo source address register 2 0x01c1 0788 dfcnt2 edma3 tc1 destination fifo count register 2 0x01c1 078c dfdst2 edma3 tc1 destination fifo destination address register 2 0x01c1 0790 dfbidx2 edma3 tc1 destination fifo b-index register 2 0x01c1 0794 dfmpprxy2 edma3 tc1 destination fifo memory protection proxy register 2 0x01c1 0798 - 0x01c1 07bf - reserved 0x01c1 07c0 dfopt3 edma3 tc1 destination fifo options register 3 0x01c1 07c4 dfsrc3 edma3 tc1 destination fifo source address register 3 0x01c1 07c8 dfcnt3 edma3 tc1 destination fifo count register 3 0x01c1 07cc dfdst3 edma3 tc1 destination fifo destination address register 3 0x01c1 07d0 dfbidx3 edma3 tc1 destination fifo b-index register 3 0x01c1 07d4 dfmpprxy3 edma3 tc1 destination fifo memory protection proxy register 3 0x01c1 07d8 - 0x01c1 07ff - reserved transfer controller 2 registers 0x01c1 0800 - reserved 0x01c1 0804 tccfg edma3 tc2 configuration register 0x01c1 0808 - 0x01c1 08ff - reserved 0x01c1 0900 tcstat edma3 tc2 channel status register 0x01c1 0904 - 0x01c1 0910 - reserved 0x01c1 0914 - 0x01c1 091f - reserved 0x01c1 0920 errstat edma3 tc2 error status register 0x01c1 0924 erren edma3 tc2 error enable register 0x01c1 0928 errclr edma3 tc2 error clear register 0x01c1 092c errdet edma3 tc2 error details register 0x01c1 0930 errcmd edma3 tc2 error interrupt command register 0x01c1 0934 - 0x01c1 093f - reserved 0x01c1 0940 rdrate edma3 tc2 read command rate register 0x01c1 0944 - 0x01c1 09ff - reserved 0x01c1 0a00 - 0x01c1 0a3f - reserved 0x01c1 0a40 saopt edma3 tc2 source active options register 0x01c1 0a44 sasrc edma3 tc2 source active source address register 0x01c1 0a48 sacnt edma3 tc2 source active count register 0x01c1 0a4c sadst edma3 tc2 source active destination address register 0x01c1 0a50 sabidx edma3 tc2 active b-index register 0x01c1 0a54 sampprxy edma3 tc2 source active memory protection proxy register 0x01c1 0a58 sacntrld edma3 tc2 source active count reload register 0x01c1 0a5c sasrcbref edma3 tc2 source active source address b-reference register submit documentation feedback peripheral information and electrical specifications 137
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-7. dm6431 edma registers (continued) hex address acronym register name 0x01c1 0a60 sadstbref edma3 tc2 source active destination address b-reference register 0x01c1 0a64 - 0x01c1 0a7f - reserved 0x01c1 0a80 dfcntrld edma3 tc2 destination fifo set count reload register 0x01c1 0a84 dfsrcbref edma3 tc2 destination fifo set source address b-reference register edma3 tc2 destination fifo set destination address b-reference 0x01c1 0a88 dfdstbref register 0x01c1 0a8c - 0x01c1 0aff - reserved 0x01c1 0b00 dfopt0 edma3 tc2 destination fifo options register 0 0x01c1 0b04 dfsrc0 edma3 tc2 destination fifo source address register 0 0x01c1 0b08 dfcnt0 edma3 tc2 destination fifo count register 0 0x01c1 0b0c dfdst0 edma3 tc2 destination fifo destination address register 0 0x01c1 0b10 dfbidx0 edma3 tc2 destination fifo b-index register 0 0x01c1 0b14 dfmpprxy0 edma3 tc2 destination fifo memory protection proxy register 0 0x01c1 0b18 - 0x01c1 0b3f - reserved 0x01c1 0b40 dfopt1 edma3 tc2 destination fifo options register 1 0x01c1 0b44 dfsrc1 edma3 tc2 destination fifo source address register 1 0x01c1 0b48 dfcnt1 edma3 tc2 destination fifo count register 1 0x01c1 0b4c dfdst1 edma3 tc2 destination fifo destination address register 1 0x01c1 0b50 dfbidx1 edma3 tc2 destination fifo b-index register 1 0x01c1 0b54 dfmpprxy1 edma3 tc2 destination fifo memory protection proxy register 1 0x01c1 0b58 - 0x01c1 0b7f - reserved 0x01c1 0b80 dfopt2 edma3 tc2 destination fifo options register 2 0x01c1 0b84 dfsrc2 edma3 tc2 destination fifo source address register 2 0x01c1 0b88 dfcnt2 edma3 tc2 destination fifo count register 2 0x01c1 0b8c dfdst2 edma3 tc2 destination fifo destination address register 2 0x01c1 0b90 dfbidx2 edma3 tc2 destination fifo b-index register 2 0x01c1 0b94 dfmpprxy2 edma3 tc2 destination fifo memory protection proxy register 2 0x01c1 0b98 - 0x01c1 0bbf - reserved 0x01c1 0bc0 dfopt3 edma3 tc2 destination fifo options register 3 0x01c1 0bc4 dfsrc3 edma3 tc2 destination fifo source address register 3 0x01c1 0bc8 dfcnt3 edma3 tc2 destination fifo count register 3 0x01c1 0bcc dfdst3 edma3 tc2 destination fifo destination address register 3 0x01c1 0bd0 dfbidx3 edma3 tc2 destination fifo b-index register 3 0x01c1 0bd4 dfmpprxy3 edma3 tc2 destination fifo memory protection proxy register 3 0x01c1 0bd8 - 0x01c1 0bff - reserved table 6-8 shows an abbreviation of the set of registers which make up the parameter set for each of 128 edma events. each of the parameter register sets consist of 8 32-bit word entries. table 6-9 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. peripheral information and electrical specifications 138 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-8. edma parameter set ram hex address range description 0x01c0 4000 - 0x01c0 401f parameters set 0 (8 32-bit words) 0x01c0 4020 - 0x01c0 403f parameters set 1 (8 32-bit words) 0x01c0 4040 - 0x01c0 405f parameters set 2 (8 32-bit words) 0x01c0 4060 - 0x01c0 407f parameters set 3 (8 32-bit words) 0x01c0 4080 - 0x01c0 409f parameters set 4 (8 32-bit words) 0x01c0 40a0 - 0x01c0 40bf parameters set 5 (8 32-bit words) ... ... 0x01c0 4fc0 - 0x01c0 4fdf parameters set 126 (8 32-bit words) 0x01c0 4fe0 - 0x01c0 4fff parameters set 127 (8 32-bit words) table 6-9. parameter set entries hex offset address acronym parameter entry within the parameter set 0x0000 opt option 0x0004 src source address 0x0008 a_b_cnt a count, b count 0x000c dst destination address 0x0010 src_dst_bidx source b index, destination b index 0x0014 link_bcntrld link address, b count reload 0x0018 src_dst_cidx source c index, destination c index 0x001c ccnt c count submit documentation feedback peripheral information and electrical specifications 139
6.5 reset 6.5.1 power-on reset ( por pin) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the reset controller detects the different type of resets supported on the dm6431 device and manages the distribution of those resets throughout the device. the dm6431 device has several types of device-level global resets - power-on reset, warm reset, and max reset. table 6-10 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. see section 6.5.9 , reset electrical data/timing, for more information on the effects of each reset on the pll controllers and their clocks. table 6-10. device-level global reset types type initiator effect(s) por pin global chip reset (cold reset). activates the por signal on chip, which resets the entire chip including the emulation logic. power-on reset the power-on reset ( por) pin must be driven low during power (por) ramp of the device. device boot and configuration pin are latched. resets everything except for the emulation logic. emulator stays warm reset reset pin alive during warm reset. device boot and configuration pin are latched. same as a warm reset, except the dm6431 device boot and max reset emulator, wd timer (timer 2) configuration pins are not re-latched. in addition to device-level global resets, the psc provides the capability to cause local resets to peripherals and/or the cpu. power-on reset (por) is initiated by the por pin and is used to reset the entire chip, including the emulation logic. power-on reset is also referred to as a cold reset since the device usually goes through a power-up cycle. during power-up, the por pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. if an external 27-mhz oscillator is used on the mxi/clkin pin, the source clock should also be running at the correct frequency prior to de-asserting the por pin. note: a device power-up cycle is not required to initiate a power-on reset. the following sequence must be followed during a power-on reset. 1. wait for the power supplies to reach normal operating conditions while keeping the por pin asserted (driven low). 2. wait for the input clock source to be stable while keeping the por pin asserted (low). 3. once the power supplies and the input clock source are stable, the por pin must remain asserted (low) for a minimum of 12 mxi cycles. within the low period of the por pin, the following happens: ? the reset signals flow to the entire chip (including the emulation logic), resetting the modules on chip. ? the pll controller clocks start at the frequency of the mxi clock. the clocks are propagated throughout the chip to reset the chip synchronously. by default, both pll1 and pll2 are in reset and unlocked. the pll controllers default to pll bypass mode. ? the resetout pin stays asserted (low), indicating the device is in reset. 4. the por pin may now be deasserted (driven high). when the por pin is deasserted (high), the configuration pin values are latched and the pll controllers changed their system clocks to their default divide-down values. both pll controllers are still in pll bypass mode. other device initialization also begins. 5. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at the end of these 10 cycles, the resetout pin is deasserted (driven high). at this point: peripheral information and electrical specifications 140 submit documentation feedback
6.5.1.1 usage of por versus reset pins 6.5.1.2 latching boot and configuration pins 6.5.2 warm reset ( reset pin) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the c64x+ begins executing from dspbootaddr (determined by bootmode selection). after the reset sequence, the boot sequence begins. for more details on the boot sequence, see the using the tms320dm643x bootloader application report (literature number spraag0 ). after the boot sequence, follow the software initialization sequence described in section 3.8 , device initialization sequence after reset. por and reset are independent resets. if the device needs to go through a power-up cycle, por ( not reset) must be used to fully reset the device. in functional end-system, emulation/debugger logic is typically not needed; therefore, the recommendation for functional end-system is to use the por pin for full device reset. if reset pin is not needed, it can be pulled inactive (high) via an external pullup resistor. in a debug system, it is typically desirable to allow the reset of the device without crashing an emulation session. in this case, the user can use the por pin to achieve full device reset and use the reset pin to achieve a debug reset?which resets the entire device except emulation logic. internal to the chip, the two device reset pins reset and por are logically and?d together only for the purpose of latching device boot and configuration pins. the values on all device and boot configuration pins are latched into the bootcfg register when the logical and of reset and por transitions from low-to-high. a warm reset is activated by driving the reset pin active low. this resets everything in the device except the emulation logic. an emulator session will stay alive during warm reset. for more information on por vs. reset usage, see section 6.5.1.1 , usage of por versus reset pins and section 6.5.1.2 , latching boot and configuration pins. the following sequence must be followed during a warm reset: 1. power supplies and input clock source should already be stable. 2. the reset pin must be asserted (low) for a minimum of 12 mxi cycles. within the low period of the reset pin, the following happens: ? the reset signals flow to the entire chip resetting all the modules on chip, except the emulation logic. ? the pll controllers are reset thereby, switching back to pll bypass mode and resetting all their registers to default values. both pll1 and pll2 are placed in reset and lose lock. ? the resetout pin becomes asserted (low), indicating the device is in reset. 3. the reset pin may now be deasserted (driven high). when the reset pin is deasserted (high), the configuration pin values are latched and the pll controllers changed their system clocks to their default divide-down values. both pll controllers are still in pll bypass mode. other device initialization also begins. 4. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at the end of these 10 cycles, the resetout pin is deasserted (driven high). submit documentation feedback peripheral information and electrical specifications 141
6.5.3 maximum reset tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com at this point: ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the c64x+ begins executing from dspbootaddr (determined by bootmode selection). after the reset sequence, the boot sequence begins. for more details on the boot sequence, see the using the tms320dm643x bootloader application report (literature number spraag0 )). after the boot sequence, follow the software initialization sequence described in section 3.8 , device initialization sequence after reset. a maximum (max) reset is initiated by the emulator or the watchdog timer (timer 2). the effects are the same as a warm reset, except the device boot and configuration pins are not re-latched. the emulator initiates a maximum reset via the icepick module. this icepick initiated reset is non-maskable. when the watchdog timer counter reaches zero, this will also initiate a maximum reset to recover from a runaway condition. the watchdog timeout reset condition is masked if the timerctl.wdrst bit is cleared to "0". to invoke the maximum reset via the icepick module, the user can perform the following from the code composer studio? ide menu: debug ? advanced resets ? system reset this is the max reset sequence: 1. max reset is initiated by the emulator or the watchdog timer. during this time, the following happens: ? the reset signals flow to the entire chip resetting all the modules on chip except the emulation logic. ? the pll controllers are reset thereby, switching back to pll bypass mode and resetting all their registers to default values. both pll1 and pll2 are placed in reset and lose lock. ? the resetout pin becomes asserted (low), indicating the device is in reset. 2. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at the end of these 10 cycles, the resetout pin is deasserted (driven high). at this point: ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the c64x+ begins executing from dspbootaddr (determined by bootmode selection). after the reset sequence, the boot sequence begins. since the boot and configuration pins are not latched with a max reset, the previous values (as shown in the bootcfg register) are used to select the boot mode. for more details on the boot sequence, see the using the tms320dm643x bootloader application report (literature number spraag0 ). after the boot sequence, follow the software initialization sequence described in section 3.8 , device initialization sequence after reset. 142 peripheral information and electrical specifications submit documentation feedback
6.5.4 cpu local reset 6.5.5 peripheral local reset 6.5.6 reset priority 6.5.7 reset controller register 6.5.8 pin behaviors at reset tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the c64x+ dsp cpu has an internal reset input that allows a host to control it. this reset is configured through a register bit (mdctl[39]. lrst) in the power sleep controller (psc) module. when in c64x+ local reset, the slave dma port on c64x+ will remain active and the internal memory will be accessible. for procedures on asserting and de-asserting cpu local reset by the host, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). for information on peripheral selection at the rising edge of por or reset, see section 3 , device configurations of this data manual. the user can configure the local reset and clock state of a peripheral through programming the psc. table 6-4 , dm6431 lpsc assignments identifies the lpsc numbers and the peripherals capable of being locally reset by the psc. for more detailed information on the programming of these peripherals by the psc, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). if any of the above reset sources occur simultaneously, the pllc only processes the highest priority reset request. the reset request priorities are as follows (high to low): power-on reset maximum reset warm reset cpu reset the reset type status (rstype) register (01c4 00e4) is the only register for the reset controller. this register falls in the same memory range as the pll1 controller registers (see table 6-18 for the pll1 controller registers (including reset controller)). for more details on the rstype register, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). during normal operations, pins are controlled by the respective peripheral selected in the pinmux0 or pinmux1 register. during device level global reset, the pin behaves as follows: multiplexed boot and configuration pins these pins are forced 3-stated when resetout is asserted (low). this is to ensure the proper boot and configuration values can be latched on these multiplexed pins. this is particularly useful in the case where the boot and configuration values are driven by an external control device. after resetout is deasserted (high), these pins are controlled by their respective default peripheral. boot and configuration pins group: gp[28], gp[27], gp[26]/(fastboot), gp[25]/(bootmode3), gp[24]/(bootmode2), gp[23]/(bootmode1), gp[22]/(bootmode0), em_a[4]/gp[10]/(aeaw2/pllms2), em_a[1]/(ale)/gp[9]/(aeaw1/pllms1), em_a[2]/(cle)/gp[8]/(aeaw0/pllms0), em_a[0]/gp[7]/(aem2), em_ba[0]/gp[6]/(aem1), and em_ba[1]/gp[5]/(aem0). for information on whether external pullup/pulldown resistors should be used on the boot and configuration pins, see section 3.9.1 , pullup/pulldown resistors. submit documentation feedback peripheral information and electrical specifications 143
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com default power down pins as discussed in section 3.2 , power considerations, the vdd3p3v_pwdn register controls power to the 3.3-v pins. the vdd3p3v_pwdn register defaults to powering down some 3.3-v pins to save power. for more details on the vdd3p3v_pwdn register and which 3.3-v pins default to powerup or powerdown, section 3.2 , power considerations. the pins that default to powerdown, are both reset to powerdown and high-impedance. they remain in that state until configured otherwise by vdd3p3_pwdn and pinmux0/pinmux1 programming. default power down pin group: gp[4]/pwm1, aclkr0/clkx0/gp[99], afsr0/dr0/gp[100], ahclkr0/clkr0/gp[101], axr0[3]/fsr0/gp[102], axr0[2]/fsx0/gp[103], axr0[1]/dx0/gp[104], axr0/gp[105], aclkx0/gp[106], afsx0/gp[107], ahclkx0/gp[108], amutein0/gp[109], amute0/gp[110], hecc_tx/tout1l/gp[55], hecc_rx/tinp1l/gp[56], clks0/tout0l/gp[97], tinp0l/gp[98], urxd0/gp[85], utxd0/gp[86], ucts0/gp[87], and urts0/pwm0/gp[88]. all other pins during resetout assertion (low), all other pins are controlled by the default peripheral. the default peripheral is determined by the default settings of the pinmux0 or pinmux1 registers. some of the pinmux0/pinmux1 settings are determined by configuration pins latched at reset. to determine the reset behavior of these pins, see section 3.7 , multiplexed pin configurations and read the rest of the this subsection to understand how that default peripheral controls the pin. the reset behaviors for all these other pins are categorized as follows (also see figure 6-7 and figure 6-8 in section 6.5.9 , reset electrical data/timing): z+/low group (z longer-to-low group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. these pins remain 3-stated throughout resetout assertion. when resetout is deasserted, these pins drive a logic low. z+/high group (z longer-to-high group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. these pins remain 3-stated throughout resetout assertion. when resetout is deasserted, these pins drive a logic high. z+/invalid group (z longer-to-invalid group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. these pins remain 3-stated throughout resetout assertion. when resetout is deasserted, these pins drive an invalid value until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). z group: these pins are 3-stated by default, and these pins remain 3-stated throughout resetout assertion. when resetout is deasserted, these pins remain 3-stated until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). low group: these pins are low by default, and remain low until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). high group: these pins are high by default, and remain high until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). z/low group (z-to-low group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. when the reset source is deasserted, these pins drive a logic low. z/high group (z-to-high group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. when reset source is deasserted, these pins drive a logic high. clock group: these clock pins are toggling by default. they paused momentarily before resetout is deasserted (high). the only pin in the clock group is clkout0. this is a list of possible default peripherals and how they control the pins during reset: gpio: all gpio pins behave according to z group. note: the following emifa list only includes pins that can default to function as emifa signals. emifa: these emifa signals are multiplexed with boot and configuration pins: em_a[4], em_a[2:0], peripheral information and electrical specifications 144 submit documentation feedback
6.5.9 reset electrical data/timing tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 em_ba[0], em_ba[1]; therefore, they are forced 3-stated throughout resetout. ? z+/low group: em_a[4], em_a[2:0] ? z+/high group: em_ba[0], em_ba[1], em_oe, em_we ? z+/invalid group: em_d[7:0] ? z/low group: em_a[21:5], em_a[3], em_r/ w ? z/high group: em_cs2 ? z group: em_wait/(rdy/ bsy) ddr2 memory controller: ? clock group: ddr_clk, ddr_clk ? ddr2 z group: ddr_dqm[1:0], ddr_dqs[1:0], ddr_d[15:0] ? ddr2 low group: ddr_cke, ddr_ba[2:0], ddr_a[12:0] ? ddr2 high group: ddr_cs, ddr_we, ddr_ras, ddr_cas i2c: all i2c pins behave according to z group. jtag: tdo, emu0, and emu1 pins behave according to z group. tck, tdi, tms, and trst are input-only pins. clock: clkout0 for more information on the pin behaviors during device-level global reset, see figure 6-7 and figure 6-8 in section 6.5.9 , reset electrical data/timing. note: if a configuration pin must be routed out from the device, the internal pullup/pulldown (ipu/ipd) resistor should not be relied upon; ti recommends the use of an external pullup/pulldown resistor. table 6-11. timing requirements for reset (see figure 6-7 and figure 6-8 ) -3/-3q/-3s no. unit min max 1 t w(reset) pulse duration, por low or reset low 12c (1) ns setup time, boot and configuration pins valid before por high or reset 4 t su(config) 12c (1) ns high (2) hold time, boot and configuration pins valid after por high or reset 5 t h(config) 0 ns high (2) (1) c = 1/mxi clock frequency in ns. the device clock source must be stable and at a valid frequency prior to meeting the t w(reset) requirement. (2) for the list of boot and configuration pins, see table 2-5 , boot terminal functions. table 6-12. switching characteristics over recommended operating conditions during reset (1) (see figure 6-8 ) -3/-3q/-3s no. parameter unit min max 2 t d(rsth-rstouth) delay time, por high or reset high to resetout high 1900c ns 3 t w(pause) pulse duration, sysclks paused (low) before resetout high 10c 10c ns 6 t d(rstl-iv) delay time, por low or reset low to pins invalid 20 ns 7 t d(rsth-v) delay time, por high or reset high to pins valid 20 ns 8 t d(rstouth-v) delay time, resetout high to pins valid 0 ns 9 t d(rstouth-iv) delay time, resetout high to pins invalid 12c ns (1) c = 1/clkin1 clock frequency in ns. submit documentation feedback peripheral information and electrical specifications 145
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 6-7 shows the power-up timing. figure 6-8 shows the warm reset ( reset) timing. max reset timing is identical to warm reset timing, except the boot and configuration pins are not relatched and the bootcfg register retains its previous value latched before the max reset was initiated. 146 peripheral information and electrical specifications submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 a. power supplies and mxi must be stable before the start of t w(reset). . b. pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. for more details on what pin group (e.g., z group, z/low group, z/high group, etc.) each pin belongs to, see section 6.5.8 , pin behaviors at reset. figure 6-7. power-up timing (b) submit documentation feedback peripheral information and electrical specifications 147 mxi (a) por reset resetout sysclkrefclk (pllc1) sysclk1 sysclk2 sysclk3 clkout0 boot and configuration pins config z+/low group (z longer-to-low) z+/high group (z longer-to-low) z group power supplies ramping power supplies stable hi-zhi-z hi-z clock source stable 1 4 5 2 3 88 8 ddr2 z group ddr2 low group ddr2 high group driven or hi-z z/high group (z-to-high) z/low group (z-to-low) 7 7 7 7 7 z+/invalid group (z longer-to-invalid) hi-z 9 invalid
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com a. pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. for more details on what pin group (e.g., z group, z/low group, z/high group, etc.) each pin belongs to, see section 6.5.8 , pin behaviors at reset. figure 6-8. warm reset ( reset) timing (a) peripheral information and electrical specifications 148 submit documentation feedback mxi por reset resetout sysclkrefclk (pllc1) sysclk1 sysclk2 sysclk3 clkout0 boot and configuration pins config power supplies stable 1 4 5 2 3 pll1 clock div1 clockdiv3 clock div6 clock driven or hi-z 8 6 driven or hi-z z+/low group (z longer-to-low) z+/high group (z longer-to-high) z group 8 ddr2 z group ddr2 low group ddr2 high group z/high group (z-to-high) 7 z/low group (z-to-low) 7 driven or hi-z driven or hi-zdriven or hi-z 66 6 6 6 8 z+/invalid group (z longer-to-invalid) 9 invalid
6.6 external clock input from mxi/clkin pin 6.6.1 clock input option 1?crystal 6.6.2 clock input option 2?1.8-v lvcmos-compatible clock input tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the dm6431 device includes two options to provide an external clock input: use an on-chip oscillator with external crystal. use an external 1.8-v lvcmos-compatible clock input. the optimal external clock input frequency is 27 mhz. section 6.6.1 provides more details on option 1, using an on-chip oscillator with external crystal. section 6.6.2 provides details on option 2, using an external 1.8-v lvcmos-compatible clock input. in this option, a crystal is used as the external clock input to the dm6431. the 27-mhz oscillator provides the reference clock for all dm6431 subsystems and peripherals. the on-chip oscillator requires an external 27-mhz crystal connected across the mxi and mxo pins, along with two load capacitors, as shown in figure 6-9 . the external crystal load capacitors must be connected only to the 27-mhz oscillator ground pin (mxv ss ). do not connect to board ground (v ss ). the mxv dd pin can be connected to the same 1.8 v power supply as dv ddr2 . figure 6-9. 27-mhz system oscillator the load capacitors, c1 and c2, should be chosen such that the equation is satisfied (typical values are c1 = c2 = 10 pf). c l in the equation is the load specified by the crystal manufacturer. all discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (mxi and mxo) and to the mxv ss pin. table 6-13. input requirements for crystal parameter min typ max unit start-up time (from power up until oscillating at stable frequency of 27 4 ms mhz) oscillaton frequency 27 mhz esr 60 w in this option, a 1.8-v lvcmos-compatible clock input is used as the external clock input to the dm6431. the external connections are shown in figure 6-10 . the mxi/clkin pin is connected to the 1.8-v lvcmos-compatible clock source. the mxo pin is left unconnected. the mxv ss pin is connected to board ground (v ss ). the mxv dd pin can be connected to the same 1.8-v power supply as dv ddr2 . submit documentation feedback peripheral information and electrical specifications 149 mxi/clkin mxo c1 c2 crystal 27 mhz mxv ss 1.8 v mxv dd c l c 1 c 2 ( c 1 c 2 )
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 6-10. 1.8-v lvcmos-compatible clock input the clock source must meet the mxi/clkin timing requirements in section 6.7.4 , clock pll electrical data/timing (input and output clocks). 150 peripheral information and electrical specifications submit documentation feedback mxi/clkin mxo nc mxv ss 1.8 v mxv dd
6.7 clock plls 6.7.1 pll1 and pll2 tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 there are two independently controlled plls on dm6431. pll1 generates the frequencies required for the dsp, dma, vpfe, and other peripherals. pll2 generates the frequencies required for the ddr2 interface. the recommended reference clock for both plls is the 27-mhz crystal input. both pll1 and pll2 power is supplied externally via the 1.8 v pll power-supply pin (pll pwr18 ). an external emi filter circuit must be added to pll pwr18 , as shown in figure 6-11 . the 1.8-v supply of the emi filter must be from the same 1.8-v power plane supplying the device?s 1.8-v i/o power-supply pins (dv dddr2 ). ti recommends emi filter manufacturer murata, part number nfm18cc222r1c3. all pll external components (c1, c2, and the emi filter) must be placed as close to the device as possible. for the best performance, ti recommends that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown in figure 6-11 . for reduced pll jitter, maximize the spacing between switching signals and the pll external components (c1, c2, and the emi filter). figure 6-11. pll1 and pll2 external connection the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see section 6.7.4 , clock pll electrical data/timing (input and output clocks). there is an allowable range for pll multiplier (pllm). there is a minimum and maximum operating frequency for mxi/clkin, pllout, and the device clocks (sysclks). the pll controllers must be configured not to exceed any of these constraints documented in this section (certain combinations of external clock inputs, internal dividers, and pll multiply ratios might not be supported). for these constraints (ranges), see table 6-14 through table 6-16 . table 6-14. pll1 and pll2 multiplier ranges pll multiplier (pllm) min max pll1 multiplier x14 x30 pll2 multiplier x14 x32 submit documentation feedback peripheral information and electrical specifications 151 pll pwr18 c2 c1 emi filter +1.8 v 0.01 f dm643x pll2 pll1 0.1 f
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-15. pllc1 clock frequency ranges clock signal name min max unit mxi/clkin (1) 20 30 mhz pllout at 1.2-v cv dd 300 600 mhz sysclk1 (clkdiv1 domain) -3/-3q/-3s devices 300 mhz (1) mxi/clkin input clock is used for both pll controllers (pllc1 and pllc2). table 6-16. pllc2 clock frequency ranges clock signal name min max unit mxi/clkin (1) 20 30 mhz pllout at 1.2-v cv dd 300 900 mhz pll2_sysclk1 (to ddr2 phy) 266 mhz (1) mxi/clkin input clock is used for both pll controllers (pllc1 and pllc2). both pll1 and pll2 have stabilization, lock, and reset timing requirements that must be followed. the pll stabilization time is the amount of time that must be allotted for the internal pll regulators to become stable after the pll is powered up (after pllctl.pllpwrdn bit goes through a 1-to-0 transition). the pll should not be operated until this stabilization time has expired. this stabilization step must be applied after these resets?a power-on reset, a warm reset, or a max reset, as the pllctl.pllpwrdn bit resets to a "1". for the pll stabliziation time value, see table 6-17 . the pll reset time is the amount of wait time needed for the pll to properly reset (writing pllrst = 0) before bringing the pll out of reset (writing pllrst = 1). for the pll reset time value, see table 6-17 . the pll lock time is the amount of time needed from when the pll is taken out of reset (pllrst = 1 with pllen = 0) to when to when the pll controller can be switched to pll mode (pllen = 1). for the pll lock time value, see table 6-17 . table 6-17. pll1 and pll2 stabilization, lock, and reset times pll stabilization/lock/reset min typ max unit time pll stabilization time 150 m s pll lock time 2000c (1) ns pll reset time 128c (1) ns (1) c = clkin cycle time in ns. for example, when mxi/clkin frequency is 27 mhz, use c = 37. 037 ns. for details on the pll initialization software sequence, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). for more information on the clock domains and their clock ratio restrictions, see section 6.3.4 , dm6431 power and clock domains. 152 peripheral information and electrical specifications submit documentation feedback
6.7.2 pll controller register description(s) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 a summary of the pll controller registers is shown in table 6-18 . for more details, see the tms320c642x dsp phase-locked loop controller (pllc) user's guide (literature number sprues0 ). table 6-18. pll and reset controller registers memory map hex address range register acronym description pll1 controller registers 0x01c4 0800 pid peripheral id register 0x01c4 08e4 rstype reset type register 0x01c4 0900 pllctl pll controller 1 pll control register 0x01c4 0910 pllm pll controller 1 pll multiplier control register 0x01c4 0918 plldiv1 pll controller 1 divider 1 register (sysclk1) 0x01c4 091c plldiv2 pll controller 1 divider 2 register (sysclk2) 0x01c4 0920 plldiv3 pll controller 1 divider 3 register (sysclk3) 0x01c4 0924 oscdiv1 pll controller 1 oscillator divider 1 register (obsclk) [clkout0 pin] 0x01c4 0928 ? reserved 0x01c4 092c ? reserved 0x01c4 0938 pllcmd pll controller 1 command register 0x01c4 093c pllstat pll controller 1 status register (shows pllc1 status) pll controller 1 clock align control register 0x01c4 0940 alnctl (indicates which sysclks need to be aligned for proper device operation) pll controller 1 plldiv divider ratio change status register 0x01c4 0944 dchange (indicates if sysclk divide ratio has been modified) 0x01c4 0948 cken pll controller 1 clock enable control register 0x01c4 094c ckstat pll controller 1 clock status register (for all clocks except sysclkx) 0x01c4 0950 systat pll controller 1 sysclk status register (indicates sysclk on/off status) 0x01c4 0960 ? reserved 0x01c4 0964 ? reserved pll2 controller registers 0x01c4 0c00 pid peripheral id register 0x01c4 0d00 pllctl pll controller 2 pll control register 0x01c4 0d10 pllm pll controller 2 pll multiplier control register 0x01c4 0d18 plldiv1 pll controller 2 divider 1 register (sysclk1) 0x01c4 0d1c ? reserved 0x01c4 0d20 - 0x01c4 0d2c ? reserved 0x01c4 0d2c bpdiv pll controller 2 bypass divider register (sysclkbp) 0x01c4 0d38 pllcmd pll controller 2 command register 0x01c4 0d3c pllstat pll controller 2 status register (shows pllc2 status) pll controller 2 clock align control register 0x01c4 0d40 alnctl (indicates which sysclks need to be aligned for proper device operation) pll controller 2 plldiv divider ratio change status register 0x01c4 0d44 dchange (indicates if sysclk divide ratio has been modified) 0x01c4 0d48 ? reserved 0x01c4 0d4c ckstat pll controller 2 clock status register (for all clocks except sysclkx) 0x01c4 0d50 systat pll controller 2 sysclk status register (indicates sysclk on/off status) 0x01c4 0d54 - 0x01c4 0fff ? reserved submit documentation feedback peripheral information and electrical specifications 153
6.7.3 clock pll considerations with external clock sources tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com if the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power both the dm6431 device and the external clock oscillator circuit. the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see section 6.7.4 , clock pll electrical data/timing (input and output clocks). rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the device requirements in this data manual (see section 5.3 , electrical characteristics over recommended ranges of supply voltage and operating temperature and section 6.7.4 , clock pll electrical data/timing (input and output clocks). 154 peripheral information and electrical specifications submit documentation feedback
6.7.4 clock pll electrical data/timing (input and output clocks) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-19. timing requirements for mxi/clkin (-3/-3q/-3s) devices (1) (2) (3) (4) (see figure 6-12 ) -3/-3q/-3s no. unit min max 1 t c(mxi) cycle time, mxi/clkin 33. 3 50 ns 2 t w(mxih) pulse duration, mxi/clkin high 0.45c 0.55c ns 3 t w(mxil) pulse duration, mxi/clkin low 0.45c 0.55c ns 4 t t(mxi) transition time, mxi/clkin 0.05c ns 5 t j(mxi) period jitter, mxi/clkin 0.02c ns (1) the mxi/clkin frequency and pll multiply factor should be chosen such that the resulting clock frequency is within the specific range for cpu operating frequency. the resulting clock frequency should also meet the pll requirements discussed in section 6.7.1 , pll1 and pll2. for example, for a -3/-3q/-3s speed device with a 27 mhz clkin frequency, the pll multiply factor should be 22. to get a 600 mhz pll output frequency, sysclk1 should be set to a pll output frequency of divide-by-2 to get 300 mhz device speed. (2) the reference points for the rise and fall transitions are measured at v il max and v ih min. (3) for more details on the pll multiplier factors, see the tms320dm63x dmp dsp subsystem reference guide (literature number spru978 ). (4) c = clkin cycle time in ns. for example, when mxi/clkin frequency is 27 mhz, use c = 37. 037 ns. figure 6-12. mxi/clkin timing table 6-20. switching characteristics over recommended operating conditions for clkout0 (1) (2) (see figure 6-13 ) -3/-3q/-3s no. parameter unit min max 1 t c cycle time, clkout0 33.3 50 ns 2 t w(clkout0h) pulse duration, clkout0 high 0.45p 0.55p ns 3 t w(clkout0l) pulse duration, clkout0 low 0.45p 0.55p ns 4 t t(clkout0) transition time, clkout0 0.05p ns (1) the reference points for the rise and fall transitions are measured at v ol max and v oh min. (2) p = 1/clkout0 clock frequency in nanoseconds (ns). for example, when clkout0 frequency is 27 mhz, use p = 37.04 ns. figure 6-13. clkout0 timing submit documentation feedback peripheral information and electrical specifications 155 mxi/clkin 2 3 4 4 5 1 clk_out0 (divide-by-1) 4 4 2 1 3
6.8 interrupts tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the c64x+ dsp interrupt controller combines device events into 12 prioritized interrupts. the source for each of the 12 cpu interrupts is user programmable and is listed in table 6-21 . also, the interrupt controller controls the generation of the cpu exception and emulation interrupts. the nmi input to the c64x+ dsp interrupt controller is not connected internally; therefore, the nmi interrupt is not available. table 6-22 summarizes the c64x+ interrupt controller registers and memory locations. for more details on dsp interrupt controller, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). table 6-21. dm6431 dsp system event mapping dsp dsp system system acronym source acronym source event event number number 0 evt0 c64x+ int ctl 0 64 gpio0 gpio 1 evt1 c64x+ int ctl 1 65 gpio1 gpio 2 evt2 c64x+ int ctl 2 66 gpio2 gpio 3 evt3 c64x+ int ctl 3 67 gpio3 gpio 4 tintl0 timer 0 ? tint12 68 gpio4 gpio 5 tinth0 timer 0 ? tint34 69 gpio5 gpio 6 tintl1 timer 1 ? tint12 70 gpio6 gpio 7 tinth1 timer 1 ? tint34 71 gpio7 gpio 8 wdint timer 2 ? tint12 72 gpiobnk0 gpio 9 emu_dtdma c64x+ emc 73 gpiobnk1 gpio 10 reserved 74 gpiobnk2 gpio 11 emu_rtdxrx c64x+ rtdx 75 gpiobnk3 gpio 12 emu_rtdxtx c64x+ rtdx 76 gpiobnk4 gpio 13 idmaint0 c64x+ emc 0 77 gpiobnk5 gpio 14 idmaint1 c64x+ emc 1 78 gpiobnk6 gpio 15 reserved 79 reserved 16 reserved 80 pwm0 pwm0 17 reserved 81 pwm1 pwm1 18 reserved 82 pwm2 pwm2 19 reserved 83 iicint0 i2c 20 reserved 84 uartint0 uart0 21 reserved 85 reserved 22 reserved 86 reserved 23 reserved 87 reserved 24 reserved 88 reserved 25 reserved 89 reserved 26 reserved 90 reserved 27 reserved 91 reserved 28 reserved 92 reserved 29 reserved 93 reserved 30 reserved 94 reserved 31 reserved 95 reserved reserved interr c64x+ interrupt controller dropped cpu 32 96 interrupt event 33 reserved 97 emc_idmaerr c64x+ emc invalid idma parameters 34 edma3cc_gint edmacc global interupt 98 reserved 35 edma3cc_int0 edmacc interrupt region 0 99 reserved 36 edma3cc_int1 edmacc interrupt region 1 100 reserved 37 edma3cc_errint edma cc error 101 reserved 38 edma3tc_errint0 edma tc0 error 102 reserved 39 edma3tc_errint1 edma tc1 error 103 reserved 40 edma3tc_errint2 edma tc2 error 104 reserved 41 pscint psc allint 105 reserved 42 reserved 106 reserved peripheral information and electrical specifications 156 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-21. dm6431 dsp system event mapping (continued) dsp dsp system system acronym source acronym source event event number number 43 emacint emac memory controller 107 reserved 44 reserved 108 reserved 45 reserved 109 reserved 46 reserved 110 reserved 47 reserved 111 reserved 48 mbxint0 mcbsp0 transmit 112 reserved 49 mbrint0 mcbsp0 receive 113 pmc_ed c64x+ pmc 50 reserved 114 reserved 51 reserved 115 reserved 52 reserved 116 umced1 c64x+ umc 1 53 ddrint ddr2 memory controller 117 umced2 c64x+ umc 2 54 emifaint emifa 118 pdcint c64x+ pdc 55 reserved 119 syscmpa c64x+ sys 56 reserved 120 pmccmpa c64x+ pmc 57 hecc0int hecc interrupt 0 121 pmcdmpa c64x+ pmc 58 hecc1int hecc interrupt 1 122 dmccmpa c64x+ dmc 59 axint0 mcasp0 transmit 123 dmcdmpa c64x+ dmc 60 arint0 mcasp0 receive 124 umccmpa c64x+ umc 61 reserved 125 umcdmpa c64x+ umc 62 reserved 126 emccmpa c64x+ emc 63 reserved 127 emcbuserr c64x+ emc table 6-22. c64x+ interrupt controller registers hex address acronym register description 0x0180 0000 evtflag0 event flag register 0 0x0180 0004 evtflag1 event flag register 1 0x0180 0008 evtflag2 event flag register 2 0x0180 000c evtflag3 event flag register 3 0x0180 0020 evtset0 event set register 0 0x0180 0024 evtset1 event set register 1 0x0180 0028 evtset2 event set register 2 0x0180 002c evtset3 event set register 3 0x0180 0040 evtclr0 event clear register 0 0x0180 0044 evtclr1 event clear register 1 0x0180 0048 evtclr2 event clear register 2 0x0180 004c evtclr3 event clear register 3 0x0180 0080 evtmask0 event mask register 0 0x0180 0084 evtmask1 event mask register 1 0x0180 0088 evtmask2 event mask register 2 0x0180 008c evtmask3 event mask register 3 0x0180 00a0 mevtflag0 masked event flag register 0 0x0180 00a4 mevtflag1 masked event flag register 1 0x0180 00a8 mevtflag2 masked event flag register 2 0x0180 00ac mevtflag3 masked event flag register 3 0x0180 00c0 expmask0 exception mask register 0 0x0180 00c4 expmask1 exception mask register 1 0x0180 00c8 expmask2 exception mask register 2 0x0180 00cc expmask3 exception mask register 3 submit documentation feedback peripheral information and electrical specifications 157
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-22. c64x+ interrupt controller registers (continued) hex address acronym register description 0x0180 00e0 mexpflag0 masked exception flag register 0 0x0180 00e4 mexpflag1 masked exception flag register 1 0x0180 00e8 mexpflag2 masked exception flag register 2 0x0180 00ec mexpflag3 masked exception flag register 3 0x0180 0104 intmux1 interrupt mux register 1 0x0180 0108 intmux2 interrupt mux register 2 0x0180 010c intmux3 interrupt mux register 3 0x0180 0180 intxstat interrupt exception status 0x0180 0184 intxclr interrupt exception clear 0x0180 0188 intdmask dropped interrupt mask register peripheral information and electrical specifications 158 submit documentation feedback
6.9 external memory interface (emif) 6.9.1 asynchronous emif (emifa) 6.9.2 nand (nand, smartmedia, xd) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 dm6431 supports several memory and external device interfaces, including: asynchronous emif (emifa) for interfacing to nor flash, sram, etc. nand flash the dm6431 asynchronous emif (emifa) provides an 8-bit data bus, an address bus width up to 24-bits, and 4 chip selects, along with memory control signals. these signals are multiplexed between these peripherals: emifa and nand interfaces vpfe (ccdc) gpio the emifa interface provides both the asynchronous emif and nand interfaces. four chip selects are provided and each are individually configurable to provide either emifa or nand support. the nand features supported are as follows. nand flash on up to 4 asynchronous chip selects. 8-bit data bus width programmable cycle timings. performs ecc calculation. nand mode also supports smartmedia and xd memory cards boot rom supports booting of the dm6431 from nand flash located at cs2 the memory map for emifa and nand registers is shown in table 6-23 . for more details on the emifa and nand interfaces, see section 2.9 , documentation support for the link to the tms320dm643x dmp peripherals overview reference guide (literature number spru983 ) for the tms320dm643x asynchronous external memory interface (emif) user's guide (literature number spru984 ). submit documentation feedback peripheral information and electrical specifications 159
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-23. emifa/nand registers hex address range acronym register name 0x01e0 0000 rcsr revision code and status register 0x01e0 0004 awccr asynchronous wait cycle configuration register 0x01e0 0008 - 0x01e0 000f - reserved 0x01e0 0010 a1cr asynchronous 1 configuration register (cs2 space) 0x01e0 0014 a2cr asynchronous 2 configuration register (cs3 space) 0x01e0 0018 a3cr asynchronous 3 configuration register (cs4 space) 0x01e0 001c a4cr asynchronous 4 configuration register (cs5 space) 0x01e0 0020 - 0x01e0 003f - reserved 0x01e0 0040 eirr emif interrupt raw register 0x01e0 0044 eimr emif interrupt mask register 0x01e0 0048 eimsr emif interrupt mask set register 0x01e0 004c eimcr emif interrupt mask clear register 0x01e0 0050 - 0x01e0 005f - reserved 0x01e0 0060 nandfcr nand flash control register 0x01e0 0064 nandfsr nand flash status register 0x01e0 0070 nandf1ecc nand flash 1 ecc register (cs2 space) 0x01e0 0074 nandf2ecc nand flash 2 ecc register (cs3 space) 0x01e0 0078 nandf3ecc nand flash 3 ecc register (cs4 space) 0x01e0 007c nandf4ecc nand flash 4 ecc register (cs5 space) 0x01e0 0080 - 0x01e0 0fff - reserved peripheral information and electrical specifications 160 submit documentation feedback
6.9.3 emifa electrical data/timing tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-24. timing requirements for asynchronous memory cycles for emifa module (1) (see figure 6-14 and figure 6-15 ) -3/-3q/-3s no. unit min nom max reads and writes 2 t w(em_wait) pulse duration, em_wait assertion and deassertion 2e ns reads 12 t su(emdv-emoeh) setup time, em_d[7:0] valid before em_oe high 5 ns 13 t h(emoeh-emdiv) hold time, em_d[7:0] valid after em_oe high 0 ns t su(emwait- 14 setup time, em_wait asserted before em_oe high (2) 4e + 5 ns emoeh) writes t su(emwait- 28 setup time, em_wait asserted before em_we high (2) 4e + 5 ns emweh) (1) e = sysclk3 period in ns for emifa. for example, when running the dsp cpu at 300 mhz, use e = 20 ns. (2) setup before end of strobe phase (if no extended wait states are inserted) by which em_wait must be asserted to add extended wait states. figure 6-16 and figure 6-17 describe emif transactions that include extended wait states inserted during the strobe phase. however, cycles inserted as part of this extended wait period should not be counted; the 4e requirement is to the start of where the hold phase would begin if there were no extended wait cycles. submit documentation feedback peripheral information and electrical specifications 161
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-25. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module (1) (2) (see figure 6-14 and figure 6-15 ) -3/-3q/-3s no parameter unit . min nom max reads and writes 1 t d(turnaround) turn around time (ta + 1) * e ns reads (rs + rst + rh + 3 t c(emrcycle) emif read cycle time ns ta + 4) * e (3) output setup time, em_cs[5:2] low to (rs + 1) * e - 4 (rs + 1) * e + 4 ns em_oe low (ss = 0) 4 t su(emcsl-emoel) output setup time, em_cs[5:2] low to -4 4 ns em_oe low (ss = 1) output hold time, em_oe high to (rh + 1) * e - 4 (rh + 1) * e + 4 ns em_cs[5:2] high (ss = 0) 5 t h(emoeh-emcsh) output hold time, em_oe high to -4 4 ns em_cs[5:2] high (ss = 1) output setup time, em_ba[1:0] valid to 6 t su(embav-emoel) (rs + 1) * e - 4 (rs + 1) * e + 4 ns em_oe low output hold time, em_oe high to 7 t h(emoeh-embaiv) (rh + 1) * e - 4 (rh + 1) * e + 4 ns em_ba[1:0] invalid output setup time, em_a[21:0] valid to 8 t su(embav-emoel) (rs + 1) * e - 4 (rs + 1) * e + 4 ns em_oe low output hold time, em_oe high to 9 t h(emoeh-embaiv) (rh + 1) * e - 4 (rh + 1) * e + 4 ns em_a[21:0] invalid 10 t w(emoel) em_oe active low width (rst + 1) * e (3) ns delay time from em_wait deasserted 11 t d(emwaith-emoeh) 4e + 4 ns to em_oe high writes (ws + wst + wh + 15 t c(emwcycle) emif write cycle time ns ta + 4) * e (3) output setup time, em_cs[5:2] low to (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low (ss = 0) 16 t su(emcsl-emwel) output setup time, em_cs[5:2] low to -4 4 ns em_we low (ss = 1) output hold time, em_we high to (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_cs[5:2] high (ss = 0) 17 t h(emweh-emcsh) output hold time, em_we high to -4 4 ns em_cs[5:2] high (ss = 1) output setup time, em_r/ w valid to 18 t su(emrnw-emwel) (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low output hold time, em_we high to 19 t h(emweh-emrnw) (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_r/ w invalid output setup time, em_ba[1:0] valid to 20 t su(embav-emwel) (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low output hold time, em_we high to 21 t h(emweh-embaiv) (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_ba[1:0] invalid output setup time, em_a[21:0] valid to 22 t su(emav-emwel) (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low output hold time, em_we high to 23 t h(emweh-emaiv) (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_a[21:0] invalid (1) rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold, ta = turn around, ew = extend wait mode, ss = select strobe mode. these parameters are programmed via the asynchronous n configuration and asynchronous wait cycle configuration registers. (2) e = sysclk3 period in ns for emifa. for example, when running the dsp cpu at 300 mhz, use e = 20 ns. (3) when ew = 1, the emif will extend the strobe period up to 4,096 additional cycles when the em_wait pin is asserted by the external device. peripheral information and electrical specifications 162 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-25. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module (see figure 6-14 and figure 6-15 ) (continued) -3/-3q/-3s no parameter unit . min nom max 24 t w(emwel) em_we active low width (wst + 1) * e (3) ns delay time from em_wait deasserted 25 t d(emwaith-emweh) 4e + 4 ns to em_we high output setup time, em_d[7:0] valid to 26 t su(emdv-emwel) (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low output hold time, em_we high to 27 t h(emweh-emdiv) (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_d[7:0] invalid figure 6-14. asynchronous memory read timing for emif submit documentation feedback peripheral information and electrical specifications 163 em_cs[5:2] em_ba[1:0] 13 12 em_a[21:0] em_oe em_d[7:0] em_we 10 59 7 48 6 3 1 em_r/w
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com figure 6-15. asynchronous memory write timing for emif figure 6-16. em_wait read timing requirements 164 peripheral information and electrical specifications submit documentation feedback em_cs[5:2] em_ba[1:0] em_a[21:0] em_we em_d[7:0] em_oe em_r/w 15 1 1618 2022 24 17 19 21 23 26 27 em_cs[5:2] 11 asserted deasserted 2 2 em_ba[1:0] em_a[21:0] em_d[7:0] em_oe em_wait setup strobe extended due to em_wait strobe hold 14
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 6-17. em_wait write timing requirements submit documentation feedback peripheral information and electrical specifications 165 em_cs[5:2] 25 asserted deasserted 2 2 em_ba[1:0] em_a[21:0] em_d[7:0] em_we em_wait setup strobe extended due to em_wait strobe hold 28
6.9.4 ddr2 memory controller 6.9.4.1 ddr2 memory controller electrical data/timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the ddr2 memory controller is a dedicated interface to ddr2 sdram. it supports jesd79d-2a standard compliant ddr2 sdram devices and can interface to 16-bit ddr2 sdram devices. for details on the ddr2 memory controller, see the tms320dm643x dmp ddr2 memory controller user?s guide (literature number spru986 ). ddr2 sdram plays a key role in a davinci-based system. such a system is expected to require a significant amount of high-speed external memory for: buffering of input image data from sensors or video sources intermediate buffering for large raw bayer data image files while performing image processing functions buffering for intermediate data while performing video encode and decode functions storage of executable code for the dsp a memory map of the ddr2 memory controller registers is shown in table 6-26 . table 6-26. ddr2 memory controller registers hex address range acronym register name 0x01c4 004c ddrvtper ddr2 vtp enable register 0x01c4 2038 ddrvtpr ddr2 vtp register 0x2000 0000 - 0x2000 0003 - reserved 0x2000 0004 sdrstat sdram status register 0x2000 0008 sdbcr sdram bank configuration register 0x2000 000c sdrcr sdram refresh control register 0x2000 0010 sdtimr sdram timing register 0x2000 0014 sdtimr2 sdram timing register 2 0x2000 0020 pbbpr peripheral bus burst priority register 0x2000 0024 - 0x2000 00bf - reserved 0x2000 00c0 irr interrupt raw register 0x2000 00c4 imr interrupt masked register 0x2000 00c8 imsr interrupt mask set register 0x2000 00cc imcr interrupt mask clear register 0x2000 00d0 - 0x2000 00e3 - reserved 0x2000 00e4 ddrphycr ddr phy control register 0x2000 00e8 - 0x2000 00ef - reserved 0x2000 00f0 vtpiocr ddr vtp io control register 0x2000 00f4 - 0x2000 7fff - reserved the implementing ddr2 pcb layout on the tms320dm643x dmp dmsoc application report (literature number spraal6 ) specifies a complete ddr2 interface solution for the dm6431 as well as a list of compatible ddr2 devices. ti has performed the simulation and system characterization to ensure all ddr2 interface timings in this solution are met. ti only supports board designs that follow the guidelines outlined in the implementing ddr2 pcb layout on the tms320dm643x dmp dmsoc application report (literature number spraal6 ). 166 peripheral information and electrical specifications submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-27. switching characteristics over recommended operating conditions for ddr2 memory controller (1) (2) (see figure 6-18 ) -3/-3q/-3s no. parameter unit min max 1 t c(ddr_clk) cycle time, ddr_clk 7.5 8 ns (1) ddr_clk cycle time = 2 x pll2 _sysclk1 cycle time. (2) the pll2 controller must be programmed such that the resulting ddr_clk clock frequency is within the specified range. figure 6-18. ddr2 memory controller clock timing submit documentation feedback peripheral information and electrical specifications 167 ddr_clk 1
6.10 video processing sub-system (vpss) overview 6.10.1 video processing front-end (vpfe) 6.10.1.1 ccd controller (ccdc) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the dm6431 video processing sub-system (vpss) provides a video processing front end (vpfe) input interface for external imaging peripherals (i.e., image sensors, video decoders, etc.). the vpss register memory mapping is shown in table 6-28 . table 6-28. vpss register descriptions hex address range register acronym description 0x01c7 3400 pid peripheral revision and class information 0x01c7 3404 pcr vpss control register 0x01c7 3408 - reserved 0x01c7 3508 sdr_reg_exp sdram non real-time read request expand 0x01c7 350c - - reserved 0x01c7 3fff the video processing front-end (vpfe) consists of the ccd controller (ccdc). together, these modules provide dm6431 with a powerful and flexible front-end interface. this module is briefly described below: the ccdc provides an interface to image sensors and digital video sources. the vpfe register memory mapping is shown in table 6-29 . table 6-29. vpfe register address range descriptions hex address range acronym register name 0x01c7 0400 ? 0x01c7 07ff ccdc vpfe ? ccd controller 0x01c7 3400 ? 0x01c7 3fff vpss vpss shared buffer logic registers the ccdc receives raw image/video data from sensors (cmos or ccd) or yuv video data in numerous formats from video decoder devices. the following features are supported by the ccdc module. conventional bayer pattern format (either 8- or 10-bit). generates hd/vd timing signals and field id to an external timing generator or can synchronize to an external timing generator. interface to progressive and interlaced sensors. rec656/ccir-656 standard (ycbcr 4:2:2 format, either 8- or 10-bit). 8-bit ycbcr 4:2:2 format with discrete h and vsync signals. optical black clamping signal generation. shutter signal control. digital clamping and black level compensation. 10-bit to 8-bit a-law compression. low-pass filter prior to writing to sdram. if this filter is enabled, 2 pixels each in the left and right edges of each line are cropped from the output. output range from 10-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area). downsampling via programmable culling patterns. control output to the ddr2 via an external write enable signal. up to 16k pixels (image size) in both the horizontal and vertical direction. the ccdc register memory mapping is shown in table 6-30 . peripheral information and electrical specifications 168 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-30. ccdc register descriptions hex address range register acronym description 0x01c7 0400 pid peripheral revision and class information 0x01c7 0404 pcr peripheral control register 0x01c7 0408 syn_mode sync and mode set register 0x01c7 040c hd_vd_wid hd and vd signal width 0x01c7 0410 pix_lines number of pixels in a horizontal line and number of lines in a frame 0x01c7 0414 horz_info horizontal pixel information 0x01c7 0418 vert_start vertical line - settings for the starting pixel 0x01c7 041c vert_lines number of vertical lines 0x01c7 0420 culling culling information in horizontal and vertical directions 0x01c7 0424 hsize_off horizontal size 0x01c7 0428 sdofst sdram/ddram line offset 0x01c7 042c sdr_addr sdram address 0x01c7 0430 clamp optical black clamping settings 0x01c7 0434 dcsub dc clamp 0x01c7 0438 colptn ccd color pattern 0x01c7 043c blkcmp black compensation 0x01c7 0440 - reserved 0x01c7 0444 - reserved 0x01c7 0448 vdint vd interrupt timing 0x01c7 044c alaw a-law setting 0x01c7 0450 rec656if rec656 interface 0x01c7 0454 ccdcfg ccd configuration 0x01c7 0458 fmtcfg data reformatter/video port configuration 0x01c7 045c fmt_horz data reformatter/video input interface horizontal information 0x01c7 0460 fmt_vert data reformatter/video input interface vertical information 0x01c7 0464 fmt_addr0 address pointer 0 setup 0x01c7 0468 fmt_addr1 address pointer 1 setup 0x01c7 046c fmt_addr2 address pointer 2 setup 0x01c7 0470 fmt_addr3 address pointer 3 setup 0x01c7 0474 fmt_addr4 address pointer 4 setup 0x01c7 0478 fmt_addr5 address pointer 5 setup 0x01c7 047c fmt_addr6 address pointer 6 setup 0x01c7 0480 fmt_addr7 address pointer 7 setup 0x01c7 0484 prgeven_0 program entries 0-7 for even line 0x01c7 0488 rrgeven_1 program entries 8-15 for even line 0x01c7 048c prggodd_0 program entries 0-7 for odd line 0x01c7 0490 prggodd_1 program entries 8-15 for odd line 0x01c7 0494 vp_out video port output settings submit documentation feedback peripheral information and electrical specifications 169
6.10.1.2 vpfe electrical data/timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-31. timing requirements for vpfe pclk master/slave mode (1) (see figure 6-19 ) -3/-3q/-3s no. unit min max 1 t c(pclk) cycle time, pclk 10.204 ns 2 t w(pclkh) pulse duration, pclk high 0.4p ns 3 t w(pclkl) pulse duration, pclk low 0.4p ns 4 t t(pclk) transition time, pclk 7 ns (1) p = pclk period in ns. figure 6-19. vpfe pclk timing table 6-32. timing requirements for vpfe (ccd) slave mode (1) (see figure 6-20 ) -3/-3q/-3s no. unit min max 5 t su(ccdv-pclk) setup time, ccd valid before pclk edge 4.5 ns 6 t h(pclk-ccdv) hold time, ccd valid after pclk edge 1 ns 7 t su(hdv-pclk) setup time, hd valid before pclk edge 4.5 ns 8 t h(pclk-hdv) hold time, hd valid after pclk edge 1 ns 9 t su(vdv-pclk) setup time, vd valid before pclk edge 4.5 ns 10 t h(pclk-vdv) hold time, vd valid after pclk edge 1 ns 11 t su(c_wev-pclk) setup time, c_we valid before pclk edge 4.5 ns 12 t h(pclk-c_wev) hold time, c_we valid after pclk edge 1 ns 13 t su(c_fieldv-pclk) setup time, c_field valid before pclk edge 4.5 ns 14 t h(pclk-c_fieldv) hold time, c_field valid after pclk edge 1 ns (1) the vpfe may be configured to operate in either positive or negative edge clocking mode. when in positive edge clocking mode the rising edge of pclk is referenced. when in negative edge clocking mode the falling edge of pclk is referenced. peripheral information and electrical specifications 170 submit documentation feedback pclk 2 1 3 4 4
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 6-20. vpfe (ccd) slave mode input data timing table 6-33. timing requirements for vpfe (ccd) master mode (1) (see figure 6-21 ) -3/-3q/-3s no. unit min max 15 t su(ccdv-pclk) setup time, ccd valid before pclk edge 4.5 ns 16 t h(pclk-ccdv) hold time, ccd valid after pclk edge 1 ns 23 t su(cwev-pclk) setup time, c_we valid before pclk edge 4.5 ns 24 t h(pclk-cwev) hold time, c_we valid after pclk edge 1 ns (1) the vpfe may be configured to operate in either positive or negative edge clocking mode. when in positive edge clocking mode the rising edge of pclk is referenced. when in negative edge clocking mode the falling edge of pclk is referenced. figure 6-21. vpfe (ccd) master mode input data timing submit documentation feedback peripheral information and electrical specifications 171 pclk (positive edge clocking) pclk (negative edge clocking) 7, 9 hd/vd ccd[15:0] 8, 10 1 1, 13 12, 14 5 6 c_we/c_field pclk (positive edge clocking) 15 16 23 24 ccd[15:0] c_we/c_field pclk (positive edge clocking)
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-34. switching characteristics over recommended operating conditions for vpfe (ccd) master mode (1) (see figure 6-22 ) -3/-3q/-3s no. parameter unit min max 18 t d(pclk-hdv) delay time, pclk edge to hd valid 2 9.5 ns 20 t d(pclk-vdv) delay time, pclk edge to vd valid 2 9.5 ns 22 t d(pclk-c_fieldv) delay time, pclk edge to c_field valid 2 9.5 ns (1) the vpfe may be configured to operate in either positive or negative edge clocking mode. when in positive edge clocking mode the rising edge of pclk is referenced. when in negative edge clocking mode the falling edge of pclk is referenced. figure 6-22. vpfe (ccd) master mode control output data timing 172 peripheral information and electrical specifications submit documentation feedback pclk 18 20 22 hd vd c_field
6.11 universal asynchronous receiver/transmitter (uart) 6.11.1 uart peripheral register description(s) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the dm6431 device has one uart peripheral (uart0). uart0 has the following features: 16-byte storage space for both the transmitter and receiver fifos 1, 4, 8, or 14 byte selectable receiver fifo trigger level for autoflow control and dma dma signaling capability for both received and transmitted data programmable auto-rts and auto-cts for autoflow control frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates prioritized interrupts programmable serial data formats ? 5, 6, 7, or 8-bit characters ? even, odd, or no parity bit generation and detection ? 1, 1.5, or 2 stop bit generation false start bit detection line break generation and detection internal diagnostic capabilities ? loopback controls for communications link fault isolation ? break, parity, overrun, and framing error simulation modem control functions (cts, rts) the uart0 registers are listed in table 6-35 . table 6-35. uart0 register descriptions hex address range acronym register name 0x01c2 0000 rbr uart0 receiver buffer register (read only) 0x01c2 0000 thr uart0 transmitter holding register (write only) 0x01c2 0004 ier uart0 interrupt enable register 0x01c2 0008 iir uart0 interrupt identification register (read only) 0x01c2 0008 fcr uart0 fifo control register (write only) 0x01c2 000c lcr uart0 line control register 0x01c2 0010 mcr uart0 modem control register 0x01c2 0014 lsr uart0 line status register 0x01c2 0018 - reserved 0x01c2 001c - reserved 0x01c2 0020 dll uart0 divisor latch (lsb) 0x01c2 0024 dlh uart0 divisor latch (msb) 0x01c2 0028 pid1 peripheral identification register 1 0x01c2 002c pid2 peripheral identification register 2 0x01c2 0030 pwremu_mgmt uart0 power and emulation management register 0x01c2 0034 - 0x01c2 03ff - reserved submit documentation feedback peripheral information and electrical specifications 173
6.11.2 uart electrical data/timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-36. timing requirements for uartx receive (1) (see figure 6-23 ) -3/-3q/-3s no. unit min max 4 t w(urxdb) pulse duration, receive data bit (urxdx) [15/30/100 pf] 0.96u 1.05u ns 5 t w(urxsb) pulse duration, receive start bit [15/30/100 pf] 0.96u 1.05u ns (1) u = uart baud time = 1/programmed baud rate. table 6-37. switching characteristics over recommended operating conditions for uartx transmit (1) (see figure 6-23 ) -3/-3q/-3s no. parameter unit min max 1 f (baud) maximum programmable baud rate 128 khz 2 t w(utxdb) pulse duration, transmit data bit (utxdx) [15/30/100 pf] u - 2 u + 2 ns 3 t w(utxsb) pulse duration, transmit start bit [15/30/100 pf] u - 2 u + 2 ns (1) u = uart baud time = 1/programmed baud rate. figure 6-23. uart transmit/receive timing 174 peripheral information and electrical specifications submit documentation feedback 3 2 start bit data bits utxdx 5 data bits bit start 4 urxdx
6.12 inter-integrated circuit (i2c) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the inter-integrated circuit (i2c) module provides an interface between dm6431 and other devices compliant with philips semiconductors inter-ic bus (i 2 c-bus?) specification version 2.1. external components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the dsp through the i2c module. the i2c port does not support cbus compatible devices. the i2c port supports: compatible with philips i2c specification revision 2.1 (january 2000) fast mode up to 400 kbps (no fail-safe i/o buffers) noise filter to remove noise 50 ns or less seven- and ten-bit device addressing modes master (transmit/receive) and slave (transmit/receive) functionality events: dma, interrupt, or polling slew-rate limited open-drain output buffers figure 6-24. i2c module block diagram for more detailed information on the i2c peripheral, see section 2.9 , documentation support section of this document for the tms320dm643x dmp peripherals overview reference guide (literature number spru983). submit documentation feedback peripheral information and electrical specifications 175 clock prescale icpsc peripheral clock(dsp/18) icclkh generator bit clock icclkl noise filter scl icxsr icdxr transmit transmit shift transmitbuffer icdrr shift icrsr receivebuffer receive receive filter sda i2c data noise icoar icsar slaveaddress control address own icmdr iccnt modedata count vector interrupt interruptstatus icivr icstr mask/status interrupt icimr interrupt/dma i2c module i2c clock shading denotes control/status registers. icemdr extendedmode
6.12.1 i2c peripheral register description(s) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-38. i2c registers hex address range acronym register name 0x1c2 1000 icoar i2c own address register 0x1c2 1004 icimr i2c interrupt mask register 0x1c2 1008 icstr i2c interrupt status register 0x1c2 100c icclkl i2c clock divider low register 0x1c2 1010 icclkh i2c clock divider high register 0x1c2 1014 iccnt i2c data count register 0x1c2 1018 icdrr i2c data receive register 0x1c2 101c icsar i2c slave address register 0x1c2 1020 icdxr i2c data transmit register 0x1c2 1024 icmdr i2c mode register 0x1c2 1028 icivr i2c interrupt vector register 0x1c2 102c icemdr i2c extended mode register 0x1c2 1030 icpsc i2c prescaler register 0x1c2 1034 icpid1 i2c peripheral identification register 1 0x1c2 1038 icpid2 i2c peripheral identification register 2 peripheral information and electrical specifications 176 submit documentation feedback
6.12.2 i2c electrical data/timing 6.12.2.1 inter-integrated circuits (i2c) timing tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-39. timing requirements for i2c timings (1) (see figure 6-25 ) -3/-3q/-3s standard no. fast mode unit mode min max min max 1 t c(scl) cycle time, scl 10 2.5 s setup time, scl high before sda low (for a repeated start 2 t su(sclh-sdal) 4.7 0.6 s condition) hold time, scl low after sda low (for a start and a repeated 3 t h(scll-sdal) 4 0.6 s start condition) 4 t w(scll) pulse duration, scl low 4.7 1.3 s 5 t w(sclh) pulse duration, scl high 4 0.6 s 6 t su(sdav-sclh) setup time, sda valid before scl high 250 100 (2) ns 7 t h(sda-scll) hold time, sda valid after scl low 0 (3) 0 (3) 0.9 (4) s pulse duration, sda high between stop and start 8 t w(sdah) 4.7 1.3 s conditions 9 t r(sda) rise time, sda 1000 20 + 0.1c b (5) 300 ns 10 t r(scl) rise time, scl 1000 20 + 0.1c b (5) 300 ns 11 t f(sda) fall time, sda 300 20 + 0.1c b (5) 300 ns 12 t f(scl) fall time, scl 300 20 + 0.1c b (5) 300 ns 13 t su(sclh-sdah) setup time, scl high before sda high (for stop condition) 4 0.6 s 14 t w(sp) pulse duration, spike (must be suppressed) 0 50 ns 15 c b (5) capacitive load for each bus line 400 400 pf (1) the i2c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered down. (2) a fast-mode i 2 c-bus? device can be used in a standard-mode i 2 c-bus system, but the requirement t su(sda-sclh) 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su(sda-sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. (3) a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. (4) the maximum t h(sda-scll) has only to be met if the device does not stretch the low period [t w(scll) ] of the scl signal. (5) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. figure 6-25. i2c receive timings submit documentation feedback peripheral information and electrical specifications 177 10 8 4 3 7 12 5 6 14 2 3 13 stop start repeated start stop sda scl 1 11 9
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-40. switching characteristics for i2c timings (1) (see figure 6-26 ) -3/-3q/-3s standard no. parameter fast mode unit mode min max min max 16 t c(scl) cycle time, scl 10 2.5 s delay time, scl high to sda low (for a repeated start 17 t d(sclh-sdal) 4.7 0.6 s condition) delay time, sda low to scl low (for a start and a repeated 18 t d(sdal-scll) 4 0.6 s start condition) 19 t w(scll) pulse duration, scl low 4.7 1.3 s 20 t w(sclh) pulse duration, scl high 4 0.6 s 21 t d(sdav-sclh) delay time, sda valid to scl high 250 100 ns 22 t v(scll-sdav) valid time, sda valid after scl low 0 0 0.9 s pulse duration, sda high between stop and start 23 t w(sdah) 4.7 1.3 s conditions 24 t r(sda) rise time, sda 1000 20 + 0.1c b (1) 300 ns 25 t r(scl) rise time, scl 1000 20 + 0.1c b (1) 300 ns 26 t f(sda) fall time, sda 300 20 + 0.1c b (1) 300 ns 27 t f(scl) fall time, scl 300 20 + 0.1c b (1) 300 ns 28 t d(sclh-sdah) delay time, scl high to sda high (for stop condition) 4 0.6 s 29 c p capacitance for each i2c pin 10 10 pf (1) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. figure 6-26. i2c transmit timings 178 peripheral information and electrical specifications submit documentation feedback 25 23 19 18 22 27 20 21 17 18 28 stop start repeated start stop sda scl 16 26 24
6.13 multichannel buffered serial port (mcbsp) 6.13.1 mcbsp peripheral register description(s) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the mcbsp provides these functions: full-duplex communication double-buffered data registers, which allow a continuous data stream independent framing and clocking for receive and transmit direct interface to industry-standard codecs, analog interface chips (aics), and other serially connected analog-to-digital (a/d) and digital-to-analog (d/a) devices external shift clock or an internal, programmable frequency shift clock for data transfer if internal clock source is used, the clkgdv field of the sample rate generator register (srgr) must always be set to a value of 1 or greater. for more detailed information on the mcbsp peripheral, see the tms320dm643x dmp multichannel buffered serial port (mcbsp) user's guide (literature number spru943 ). table 6-41. mcbsp 0 registers hex address range acronym register name comments the cpu and edma3 controller can only read 01d0 0000 drr0 mcbsp0 data receive register this register; they cannot write to it. 01d0 0004 dxr0 mcbsp0 data transmit register 01d0 0008 spcr0 mcbsp0 serial port control register 01d0 000c rcr0 mcbsp0 receive control register 01d0 0010 xcr0 mcbsp0 transmit control register 01d0 0014 srgr0 mcbsp0 sample rate generator register 01d0 0018 mcr0 mcbsp0 multichannel control register mcbsp0 enhanced receive channel enable register 01d0 001c rcere00 0 partition a/b mcbsp0 enhanced transmit channel enable register 01d0 0020 xcere00 0 partition a/b 01d0 0024 pcr0 mcbsp0 pin control register mcbsp0 enhanced receive channel enable register 01d0 0028 rcere10 1 partition c/d mcbsp0 enhanced transmit channel enable register 01d0 002c xcere10 1 partition c/d mcbsp0 enhanced receive channel enable register 01d0 0030 rcere20 2 partition e/f mcbsp0 enhanced transmit channel enable register 01d0 0034 xcere20 2 partition e/f mcbsp0 enhanced receive channel enable register 01d0 0038 rcere30 3 partition g/h mcbsp0 enhanced transmit channel enable register 01d0003c xcere30 3 partition g/h 01d0 0040 - 01d0 07ff - reserved submit documentation feedback peripheral information and electrical specifications 179
6.13.2 mcbsp electrical data/timing 6.13.2.1 multichannel buffered serial port (mcbsp) timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-42. timing requirements for mcbsp (1) (see figure 6-27 ) -3/-3q/-3s no. unit min max 2 t c(ckrx) cycle time, clkr/x clkr/x ext 2p (2) (3) ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p - 1 (4) ns clkr int 14 5 t su(frh-ckrl) setup time, external fsr high before clkr low ns clkr ext 4 clkr int 6 6 t h(ckrl-frh) hold time, external fsr high after clkr low ns clkr ext 4 clkr int 14 7 t su(drv-ckrl) setup time, dr valid before clkr low ns clkr ext 4 clkr int 3 8 t h(ckrl-drv) hold time, dr valid after clkr low ns clkr ext 3.5 clkx int 14 10 t su(fxh-ckxl) setup time, external fsx high before clkx low ns clkx ext 4 clkx int 6 11 t h(ckxl-fxh) hold time, external fsx high after clkx low ns clkx ext 3 (1) clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (3) use whichever value is greater. minimum clkr/x cycle times must be met, even when clkr/x is generated by an internal clock source. the minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timing requirements. (4) this parameter applies to the maximum mcbsp frequency. operate serial clocks (clkr/x) in the reasonable range of 40/60 duty cycle. peripheral information and electrical specifications 180 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-43. switching characteristics over recommended operating conditions for mcbsp (1) (2) (see figure 6-27 ) -3/-3q/-3s no. parameter unit min max delay time, clks high to clkr/x high for internal clkr/x 1 t d(cksh-ckrxh) 3 10 ns generated from clks input 2 t c(ckrx) cycle time, clkr/x clkr/x int 2p (3) (4) (5) ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c - 2 (6) c + 2 (6) ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int -4 5.5 ns clkx int -4 5.5 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid ns clkx ext 2.5 14.5 clkx int -5.5 7.5 disable time, dx high impedance following 12 t dis(ckxh-dxhz) ns last data bit from clkx high clkx ext -2.1 16 clkx int -4 + d1 (7) 5.5 + d2 (7) 13 t d(ckxh-dxv) delay time, clkx high to dx valid ns clkx ext 2.5 + d1 (7) 14.5 + d2 (7) delay time, fsx high to dx valid fsx int -4 (8) 5 (8) 14 t d(fxh-dxv) ns only applies when in data fsx ext 1 (8) 14.5 (8) delay 0 (xdatdly = 00b) mode (1) clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) minimum delay times also represent minimum output hold times. (3) minimum clkr/x cycle times must be met, even when clkr/x is generated by an internal clock source. minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timing requirements. (4) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (5) use whichever value is greater. (6) c = h or l s = sample rate generator input clock = p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the maximum limit (see (4) above). (7) extra delay from clkx high to dx valid applies only to the first data bit of a device, if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 6p, d2 = 12p (8) extra delay from fsx high to dx valid applies only to the first data bit of a device, if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 6p, d2 = 12p submit documentation feedback peripheral information and electrical specifications 181
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com a. parameter no. 13 applies to the first data bit only when xdatdly 1 0. figure 6-27. mcbsp timing (b) table 6-44. timing requirements for fsr when gsync = 1 (see figure 6-28 ) -3/-3q/-3s no. unit min max 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns figure 6-28. fsr timing when gsync = 1 table 6-45. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 (1) (2) (see figure 6-29 ) -3/-3q/-3s no. master slave unit min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 14 2 - 3p ns (1) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. peripheral information and electrical specifications 182 submit documentation feedback bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xda tdly=00b) dx 13 (a) 13 (a) 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync)
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-45. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 (see figure 6-29 ) (continued) -3/-3q/-3s no. master slave unit min max min max 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns table 6-46. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 (1) (2) (see figure 6-29 ) -3/-3q/-3s no. parameter master (3) slave unit min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low (4) t - 4 t + 5.5 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high (5) l - 4 l + 4 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid -4 5.5 3p + 2.8 5p + 17 ns disable time, dx high impedance following 6 t dis(ckxl-dxhz) l - 6 l + 7.5 ns last data bit from clkx low disable time, dx high impedance following 7 t dis(fxh-dxhz) p + 3 3p + 17 ns last data bit from fsx high 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 1.8 4p + 17 ns (1) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 2p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = 2p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 6-29. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 submit documentation feedback peripheral information and electrical specifications 183 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 76 2 1 clkx fsx dx dr
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-47. timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 (1) (2) (see figure 6-30 ) -3/-3q/-3s no. master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 14 2 - 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns (1) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. peripheral information and electrical specifications 184 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-48. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 (1) (2) (see figure 6-30 ) -3/-3q/-3s no. parameter master (3) slave unit min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low (4) l - 4 l + 5.5 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high (5) t - 4 t + 4 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid -4 5.5 3p + 2.8 5p + 17 ns disable time, dx high impedance following 6 t dis(ckxl-dxhz) -6 7.5 3p + 2 5p + 17 ns last data bit from clkx low 7 t d(fxl-dxv) delay time, fsx low to dx valid h - 4 h + 5.5 2p + 2 4p + 17 ns (1) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 2p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = 2p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 6-30. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 table 6-49. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 (1) (2) (see figure 6-31 ) -3/-3q/-3s no. master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 14 2 - 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns (1) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. submit documentation feedback peripheral information and electrical specifications 185 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-50. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 (1) (2) (see figure 6-31 ) -3/-3q/-3s no. parameter master (3) slave unit min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high (4) t - 4 t + 5.5 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low (5) h - 4 h + 4 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid -4 5.5 3p + 2.8 5p + 17 ns disable time, dx high impedance following 6 t dis(ckxh-dxhz) h - 6 h + 7.5 ns last data bit from clkx high disable time, dx high impedance following 7 t dis(fxh-dxhz) p + 3 3p + 17 ns last data bit from fsx high 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 2 4p + 17 ns (1) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 2p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = 2p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 6-31. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 table 6-51. timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 (1) (2) (see figure 6-32 ) -3/-3q/-3s no. master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 14 2 - 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5+ 6p ns (1) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. peripheral information and electrical specifications 186 submit documentation feedback bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-52. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 (1) (2) (see figure 6-32 ) -3/-3q/-3s no. parameter master (3) slave unit min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high (4) h - 4 h + 5.5 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low (5) t - 4 t + 4 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid -4 5.5 3p + 2.8 5p + 17 ns disable time, dx high impedance following 6 t dis(ckxh-dxhz) -6 7.5 3p + 2 5p + 17 ns last data bit from clkx high 7 t d(fxl-dxv) delay time, fsx low to dx valid l - 4 l+ 5.5 2p + 2 4p + 17 ns (1) p = sysclk3 period in ns. for example, when running parts at 300 mhz, use p = 20 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 2p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = 2p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 6-32. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 submit documentation feedback peripheral information and electrical specifications 187 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr
6.14 multichannel audio serial port (mcasp0) peripheral 6.14.1 mcasp0 device-specific information tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the mcasp functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. the mcasp is useful for time-division multiplexed (tdm) stream, inter-integrated sound (i2s) protocols, and intercomponent digital audio interface transmission (dit). the dm6431 device includes one multichannel audio serial port (mcasp) interface peripheral (mcasp0). the mcasp0 is a serial port optimized for the needs of multichannel audio applications. the mcasp0 consists of a transmit and receive section. these sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. the mcasp module also includes a pool of 16 shift registers that may be configured to operate as either transmit data or receive data. the transmit section of the mcasp can transmit data in either a time-division-multiplexed (tdm) synchronous serial format or in a digital audio interface (dit) format where the bit stream is encoded for s/pdif, aes-3, iec-60958, cp-430 transmission. the receive section of the mcasp supports the tdm synchronous serial format. the mcasp can support one transmit data format (either a tdm format or dit format) and one receive format at a time. all transmit shift registers use the same format and all receive shift registers use the same format. however, the transmit and receive formats need not be the same. both the transmit and receive sections of the mcasp also support burst mode which is useful for non-audio data (for example, passing control information between two dsps). the mcasp peripheral has additional capability for flexible clock generation, and error detection/handling, as well as error management. for more detailed information on and the functionality of the mcasp0 peripheral, see the tms320dm643x dmp multichannel audio serial port (mcasp) user's guide (literature number spru980). peripheral information and electrical specifications 188 submit documentation feedback
6.14.1.1 mcasp block diagram tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 figure 6-33 illustrates the major blocks along with external signals of the mcasp0 peripheral; and shows the 4 serial data [axr] pins. figure 6-33. mcasp0 configuration submit documentation feedback peripheral information and electrical specifications 189 receive clock generator ahclkr0aclkr0 t generator clock transmit aclkx0 ahclkx0 dit ram transmit generator frame sync afsx0 detect error receive frame sync generator formatter transmit data amute0amutein0 afsr0 serializer 0 serializer 1 serializer 3 serializer 2 clock check ransmit (high- frequency) receive clock check (high- frequency) receive formatter data mcasp0 dms t ransmit dma receive individually programmable tx/rx/gpio control gpio axr0[0]axr0[1] axr0[3] axr0[2]
6.14.1.2 mcasp0 peripheral register description(s) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-53. mcasp0 control registers hex address range acronym register name 01d0 1000 pid peripheral identification register [register value: 0x0010 0101] 01d0 1004 ? reserved 01d0 1008 ? reserved 01d0 100c ? reserved 01d0 1010 pfunc pin function register 01d0 1014 pdir pin direction register 01d0 1018 ? reserved 01d0 101c ? reserved 01d0 1020 ? reserved 01d0 1024 ? 01d0 1040 ? reserved 01d0 1044 gblctl global control register 01d0 1048 amute mute control register 01d0 104c dlbctl digital loop-back control register 01d0 1050 ditctl dit mode control register 01d0 1054 ? 01d0 105c ? reserved alias of gblctl containing only receiver reset bits, allows transmit to be reset 01d0 1060 rgblctl independently from receive. 01d0 1064 rmask receiver format unit bit mask register 01d0 1068 rfmt receive bit stream format register 01d0 106c afsrctl receive frame sync control register 01d0 1070 aclkrctl receive clock control register 01d0 1074 ahclkrctl high-frequency receive clock control register 01d0 1078 rtdm receive tdm slot 0?31 register 01d0 107c rintctl receiver interrupt control register 01d0 1080 rstat status register ? receiver 01d0 1084 rslot current receive tdm slot register 01d0 1088 rclkchk receiver clock check control register 01d0 108c ? 01d0 109c ? reserved alias of gblctl containing only transmitter reset bits, allows transmit to be reset 01d0 10a0 xgblctl independently from receive. 01d0 10a4 xmask transmit format unit bit mask register 01d0 10a8 xfmt transmit bit stream format register 01d0 10ac afsxctl transmit frame sync control register 01d0 10b0 aclkxctl transmit clock control register 01d0 10b4 ahclkxctl high-frequency transmit clock control register 01d0 10b8 xtdm transmit tdm slot 0?31 register 01d0 10bc xintctl transmit interrupt control register 01d0 10c0 xstat status register ? transmitter 01d0 10c4 xslot current transmit tdm slot 01d0 10c8 xclkchk transmit clock check control register 190 peripheral information and electrical specifications submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-53. mcasp0 control registers (continued) hex address range acronym register name 01d0 10cc ? 01d0 10fc ? reserved 01d0 1100 ditcsra0 left (even tdm slot) channel status register file 01d0 1104 ditcsra1 left (even tdm slot) channel status register file 01d0 1108 ditcsra2 left (even tdm slot) channel status register file 01d0 110c ditcsra3 left (even tdm slot) channel status register file 01d0 1110 ditcsra4 left (even tdm slot) channel status register file 01d0 1114 ditcsra5 left (even tdm slot) channel status register file 01d0 1118 ditcsrb0 right (odd tdm slot) channel status register file 01d0 111c ditcsrb1 right (odd tdm slot) channel status register file 01d0 1120 ditcsrb2 right (odd tdm slot) channel status register file 01d0 1124 ditcsrb3 right (odd tdm slot) channel status register file 01d0 1128 ditcsrb4 right (odd tdm slot) channel status register file 01d0 112c ditcsrb5 right (odd tdm slot) channel status register file 01d0 1130 ditudra0 left (even tdm slot) user data register file 01d0 1134 ditudra1 left (even tdm slot) user data register file 01d0 1138 ditudra2 left (even tdm slot) user data register file 01d0 113c ditudra3 left (even tdm slot) user data register file 01d0 1140 ditudra4 left (even tdm slot) user data register file 01d0 1144 ditudra5 left (even tdm slot) user data register file 01d0 1148 ditudrb0 right (odd tdm slot) user data register file 01d0 114c ditudrb1 right (odd tdm slot) user data register file 01d0 1150 ditudrb2 right (odd tdm slot) user data register file 01d0 1154 ditudrb3 right (odd tdm slot) user data register file 01d0 1158 ditudrb4 right (odd tdm slot) user data register file 01d0 115c ditudrb5 right (odd tdm slot) user data register file 01d0 1160 ? 01d0 117c ? reserved 01d0 1180 srctl0 serializer 0 control register 01d0 1184 srctl1 serializer 1 control register 01d0 1188 srctl2 serializer 2 control register 01d0 118c srctl3 serializer 3 control register 01d0 1190 ? 01d0 11fc ? reserved 01d0 1200 xbuf0 transmit buffer for serializer 0 01d0 1204 xbuf1 transmit buffer for serializer 1 01d0 1208 xbuf2 transmit buffer for serializer 2 01d0 120c xbuf3 transmit buffer for serializer 3 01d0 1210 ? 01d0 127c ? reserved 01d0 1280 rbuf0 receive buffer for serializer 0 01d0 1284 rbuf1 receive buffer for serializer 1 01d0 1288 rbuf2 receive buffer for serializer 2 01d0 128c rbuf3 receive buffer for serializer 3 01d0 1290 ? 01d0 13ff ? reserved table 6-54. mcasp0 data registers hex address range acronym register name comments (used when rsel or xsel mcasp0 receive buffers or mcasp0 transmit buffers via bits = 0 [these bits are located 01d0 1400 ? 01d0 17ff rbuf/xbuf the peripheral data bus. in the rfmt or xfmt registers, respectively].) submit documentation feedback peripheral information and electrical specifications 191
6.14.1.3 mcasp0 electrical data/timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com 6.14.1.3.1 multichannel audio serial port (mcasp) timing table 6-55. timing requirements for mcasp (see figure 6-34 and figure 6-35 ) (1) -3/-3q/-3s no. unit min max 1 t c(ahckrx) cycle time, ahclkr/x 25 ns 2 t w(ahckrx) pulse duration, ahclkr/x high or low 10 ns 3 t c(ckrx) cycle time, aclkr/x aclkr/x ext 25 ns 4 t w(ckrx) pulse duration, aclkr/x high or low aclkr/x ext 10 ns aclkr/x int 11 ns 5 t su(frx-ckrx) setup time, afsr/x input valid before aclkr/x latches data aclkr/x ext 3 ns aclkr/x int 0 ns 6 t h(ckrx-frx) hold time, afsr/x input valid after aclkr/x latches data aclkr/x ext input 4 ns aclkr/x ext output 6 ns aclkr/x int 11 ns 7 t su(axr-ckrx) setup time, axr input valid before aclkr/x latches data aclkr/x ext 3 ns aclkr/x int 3 ns 8 t h(ckrx-axr) hold time, axr input valid after aclkr/x latches data aclkr/x ext input 4 ns aclkr/x ext output 6 ns (1) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 peripheral information and electrical specifications 192 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-56. switching characteristics over recommended operating conditions for mcasp (1) (2) (see figure 6-34 and figure 6-35 ) (3) -3/-3q/-3s no. parameter unit min max 9 t c(ahckrx) cycle time, ahclkr/x 25 ns 10 t w(ahckrx) pulse duration, ahclkr/x high or low ah - 2.5 ns aclkr/x 11 t c(ckrx) cycle time, aclkr/x 25 ns int aclkr/x 12 t w(ckrx) pulse duration, aclkr/x high or low a - 2.5 ns int aclkr/x -2.25 5.5 ns int aclkr/x 13 t d(ckrx-frx) delay time, aclkr/x transmit edge to afsx/r output valid 0 12.5 ns ext input aclkr/x 0 14 ns ext output aclkx int -2.25 5.5 ns aclkx 0 12.5 ns 14 t d(ckx-axrv) delay time, aclkx transmit edge to axr output valid ext input aclkx 0 14 ns ext output aclkr/x -4.5 8 ns int disable time, axr high impedance following last data bit from 15 t dis(ckrx-axrhz) aclkr/x transmit edge aclkr/x -4.5 12.5 ns ext (1) a = (aclkr/x period)/2 in ns. for example, when aclkr/x period is 25 ns, use a = 12.5 ns. (2) ah = (ahclkr/x period)/2 in ns. for example, when ahclkr/x period is 25 ns, use ah = 12.5 ns. (3) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 submit documentation feedback peripheral information and electrical specifications 193
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com a. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). b. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). figure 6-34. mcasp input timings 194 peripheral information and electrical specifications submit documentation feedback 8 7 4 4 3 2 2 1 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay)afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay)afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data in/receive) 6 5 aclkr/x (clkrp = clkxp = 0) (a) aclkr/x (clkrp = clkxp = 1) (b)
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 a. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). b. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). figure 6-35. mcasp output timings submit documentation feedback peripheral information and electrical specifications 195 15 14 13 13 13 13 13 13 13 12 12 11 10 10 9 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay) afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data out/t ransmit) aclkr/x (clkrp = clkxp = 0) (b) aclkr/x (clkrp = clkxp = 1) (a)
6.15 high-end controller area network controller (hecc) 6.15.1 hecc device-specific information tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the dm6431 device has a high-end controller area network controllers (hecc). the hecc uses established protocol to communicate serially with other controllers in harsh environments. the hecc is fully compliant with the controller area network (can) protocol, version 2.0b. key features of the hecc include the following: can, version 2.0b compliant 32 rx/tx message objects 32 receive identifier masks programmable wake-up on bus activity programmable interrupt scheme automatic reply to a remote request automatic re-transmission in case of error or loss of arbitration protection against reception of a new message 32-bit time stamp local network time counter programmable priority register for each message programmable transmission and reception time-out hecc/scc mode of operation standard-extended identifier self-test mode for more details on the hecc, see the tms320dm643x high-end can controller (hecc) user's guide (literature number spru981). software must not access "reserved" locations of the hecc. access to hecc "reserved" locations may hang the device. 196 peripheral information and electrical specifications submit documentation feedback
6.15.2 hecc peripheral register description(s) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-57 through table 6-60 show the high-end can controller (hecc) registers. for more detailed information, see the tms320dm643x dmp high-end can controller user?s guide (literature number spru981 ). table 6-57. hecc control and status registers hex address range acronym register name 01c2 3000 canme mailbox enable register 01c2 3004 canmd mailbox direction register 01c2 3008 cantrs transmission request set register 01c2 300c cantrr transmission request reset register 01c2 3010 canta transmission acknowledge register 01c2 3014 canaa abort acknowledge register 01c2 3018 canrmp receive message pending register 01c2 301c canrml receive message lost register 01c2 3020 canrfp remote frame pending register 01c2 3024 cangam global acceptance mask register (scc mode only) 01c2 3028 canmc master control register 01c2 302c canbtc bit-timing configuration register 01c2 3030 canes error and status register 01c2 3034 cantec transmit error counter register 01c2 3038 canrec receive error counter register 01c2 303c cangif0 global interrupt flag 0 register 01c2 3040 cangim global interrupt mask register 01c2 3044 cangif1 global interrupt flag 1 register 01c2 3048 canmim mailbox interrupt mask register 01c2 304c canmil mailbox interrupt level register 01c2 3050 canopc overwrite protection control register 01c2 3054 cantioc transmit i/o control register 01c2 3058 canrioc receive i/o control register 01c2 305c canlnt local network time register (hecc mode only) 01c2 3060 cantoc time-out control register (hecc mode only) 01c2 3064 cantos time-out status register (hecc mode only) 01c2 3068 ? 01c2 306c ? reserved 01c2 3070 canetc error test control register 01c2 3074 ? 01c2 307c ? reserved 01c2 3080 scclam0 scc local acceptance mask register 0 (scc mode only) 01c2 3084 ? 01c2 3088 ? reserved 01c2 308c ssclam3 scc local acceptance mask register 3 (scc mode only) 01c2 3090 ? 01c2 4fff ? reserved submit documentation feedback peripheral information and electrical specifications 197
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-58. hecc message object registers (1) hex address range acronym register name hecc local acceptance mask registers 01c2 5000 lam0 hecc local acceptance mask register for mailbox 0 01c2 5004 lam1 hecc local acceptance mask register for mailbox 1 01c2 5008 lam2 hecc local acceptance mask register for mailbox 2 01c2 500c lam3 hecc local acceptance mask register for mailbox 3 01c2 5010 lam4 hecc local acceptance mask register for mailbox 4 01c2 5014 lam5 hecc local acceptance mask register for mailbox 5 01c2 5018 lam6 hecc local acceptance mask register for mailbox 6 01c2 501c lam7 hecc local acceptance mask register for mailbox 7 01c2 5020 lam8 hecc local acceptance mask register for mailbox 8 01c2 5024 lam9 hecc local acceptance mask register for mailbox 9 01c2 5028 lam10 hecc local acceptance mask register for mailbox 10 01c2 502c lam11 hecc local acceptance mask register for mailbox 11 01c2 5030 lam12 hecc local acceptance mask register for mailbox 12 01c2 5034 lam13 hecc local acceptance mask register for mailbox 13 01c2 5038 lam14 hecc local acceptance mask register for mailbox 14 01c2 503c lam15 hecc local acceptance mask register for mailbox 15 01c2 5040 lam16 hecc local acceptance mask register for mailbox 16 01c2 5044 lam17 hecc local acceptance mask register for mailbox 17 01c2 5048 lam18 hecc local acceptance mask register for mailbox 18 01c2 504c lam19 hecc local acceptance mask register for mailbox 19 01c2 5050 lam20 hecc local acceptance mask register for mailbox 20 01c2 5054 lam21 hecc local acceptance mask register for mailbox 21 01c2 5058 lam22 hecc local acceptance mask register for mailbox 22 01c2 505c lam23 hecc local acceptance mask register for mailbox 23 01c2 5060 lam24 hecc local acceptance mask register for mailbox 24 01c2 5064 lam25 hecc local acceptance mask register for mailbox 25 01c2 5068 lam26 hecc local acceptance mask register for mailbox 26 01c2 506c lam27 hecc local acceptance mask register for mailbox 27 01c2 5070 lam28 hecc local acceptance mask register for mailbox 28 01c2 5074 lam29 hecc local acceptance mask register for mailbox 29 01c2 5078 lam30 hecc local acceptance mask register for mailbox 30 01c2 507c lam31 hecc local acceptance mask register for mailbox 31 message object time-stamp registers 01c2 5080 mots0 message object time-stamp register for mailbox 0 01c2 5084 mots1 message object time-stamp register for mailbox 1 01c2 5088 mots2 message object time-stamp register for mailbox 2 01c2 508c mots3 message object time-stamp register for mailbox 3 01c2 5090 mots4 message object time-stamp register for mailbox 4 01c2 5094 mots5 message object time-stamp register for mailbox 5 01c2 5098 mots6 message object time-stamp register for mailbox 6 01c2 509c mots7 message object time-stamp register for mailbox 7 01c2 50a0 mots8 message object time-stamp register for mailbox 8 01c2 50a4 mots9 message object time-stamp register for mailbox 9 01c2 50a8 mots10 message object time-stamp register for mailbox 10 01c2 50ac mots11 message object time-stamp register for mailbox 11 (1) all registers in this table apply to hecc mode only, they do not apply to scc mode. peripheral information and electrical specifications 198 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-58. hecc message object registers (continued) hex address range acronym register name 01c2 50b0 mots12 message object time-stamp register for mailbox 12 01c2 50b4 mots13 message object time-stamp register for mailbox 13 01c2 50b8 mots14 message object time-stamp register for mailbox 14 01c2 50bc mots15 message object time-stamp register for mailbox 15 01c2 50c0 mots16 message object time-stamp register for mailbox 16 01c2 50c4 mots17 message object time-stamp register for mailbox 17 01c2 50c8 mots18 message object time-stamp register for mailbox 18 01c2 50cc mots19 message object time-stamp register for mailbox 19 01c2 50d0 mots20 message object time-stamp register for mailbox 20 01c2 50d4 mots21 message object time-stamp register for mailbox 21 01c2 50d8 mots22 message object time-stamp register for mailbox 22 01c2 50dc mots23 message object time-stamp register for mailbox 23 01c2 50e0 mots24 message object time-stamp register for mailbox 24 01c2 50e4 mots25 message object time-stamp register for mailbox 25 01c2 50e8 mots26 message object time-stamp register for mailbox 26 01c2 50ec mots27 message object time-stamp register for mailbox 27 01c2 50f0 mots28 message object time-stamp register for mailbox 28 01c2 50f4 mots29 message object time-stamp register for mailbox 29 01c2 50f8 mots30 message object time-stamp register for mailbox 30 01c2 50fc mots31 message object time-stamp register for mailbox 31 message object time-out registers 01c2 5100 moto0 message object time-out register for mailbox 0 01c2 5104 moto1 message object time-out register for mailbox 1 01c2 5108 moto2 message object time-out register for mailbox 2 01c2 510c moto3 message object time-out register for mailbox 3 01c2 5110 moto4 message object time-out register for mailbox 4 01c2 5114 moto5 message object time-out register for mailbox 5 01c2 5118 moto6 message object time-out register for mailbox 6 01c2 511c moto7 message object time-out register for mailbox 7 01c2 5120 moto8 message object time-out register for mailbox 8 01c2 5124 moto9 message object time-out register for mailbox 9 01c2 5128 moto10 message object time-out register for mailbox 10 01c2 512c moto11 message object time-out register for mailbox 11 01c2 5130 moto12 message object time-out register for mailbox 12 01c2 5134 moto13 message object time-out register for mailbox 13 01c2 5138 moto14 message object time-out register for mailbox 14 01c2 513c moto15 message object time-out register for mailbox 15 01c2 5140 moto16 message object time-out register for mailbox 16 01c2 5144 moto17 message object time-out register for mailbox 17 01c2 5148 moto18 message object time-out register for mailbox 18 01c2 514c moto19 message object time-out register for mailbox 19 01c2 5150 moto20 message object time-out register for mailbox 20 01c2 5154 moto21 message object time-out register for mailbox 21 01c2 5158 moto22 message object time-out register for mailbox 22 01c2 515c moto23 message object time-out register for mailbox 23 01c2 5160 moto24 message object time-out register for mailbox 24 01c2 5164 moto25 message object time-out register for mailbox 25 submit documentation feedback peripheral information and electrical specifications 199
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-58. hecc message object registers (continued) hex address range acronym register name 01c2 5168 moto26 message object time-out register for mailbox 26 01c2 516c moto27 message object time-out register for mailbox 27 01c2 5170 moto28 message object time-out register for mailbox 28 01c2 5174 moto29 message object time-out register for mailbox 29 01c2 5178 moto30 message object time-out register for mailbox 30 01c2 517c moto31 message object time-out register for mailbox 31 table 6-59. hecc message mailbox ram (1) (2) hex address range description 01c2 4000 ? 01c2 400f mailbox 0 (4 32-bit registers) 01c2 4010 ? 01c2 401f mailbox 1 (4 32-bit registers) 01c2 4020 ? 01c2 402f mailbox 2 (4 32-bit registers) 01c2 4030 ? 01c2 403f mailbox 3 (4 32-bit registers) 01c2 4040 ? 01c2 404f mailbox 4 (4 32-bit registers) ... ... 01c2 41e0 ? 01c2 41ef mailbox 30 (4 32-bit registers) 01c2 41f0 ? 01c2 41ff mailbox 31 (4 32-bit registers) (1) this table summarizes the address ranges for the message mailboxes 0 to 31. for the contents within each message mailbox ram, see table 6-60 , message mailbox n ram entries. (2) for scc mode, only mailboxes 0 to 15 are supported. table 6-60. hecc message mailbox n ram entries (1) hex address acronym (2) mailbox register name offset (within ram) 0 midn message identifier register for mailbox n 4 mcfn message control field register for mailbox n 8 mdln message data low-word register for mailbox n c mdhn message data high-word register for mailbox n (1) for the hex address range of mailbox n, see table 6-59 , message mailbox ram. for example, message mailbox 0 occupies hex address range 0x01c2 4000 ? 0x01c2 400f. (2) the suffix "n" indicates the message mailbox number. for example, message mailbox 0 has the following message mailbox registers: mid0, mcf0, mdl0, and mdh0. peripheral information and electrical specifications 200 submit documentation feedback
6.15.3 hecc electrical data/timing tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-61. timing requirements for hecc receive (1) (see figure 6-36 ) -3/-3q/-3s no. unit min max 1 f (baud) maximum programmable baud rate 1 mbps 2 t w(hecc_rx) pulse duration, receive data bit h - 2 h + 2 ns (1) h = hecc baud time = 1/programmed baud rate. table 6-62. switching characteristics over recommended operating conditions for hecc transmit (1) (see figure 6-36 ) -3/-3q/-3s no. parameter unit min max 3 f (baud) maximum programmable baud rate 1 mbps 4 t w(hecc_tx) pulse duration, transmit data bit h - 2 h + 2 ns (1) h = hecc baud time = 1/programmed baud rate. figure 6-36. hecc transmit/receive timing submit documentation feedback peripheral information and electrical specifications 201 2 heccx_rx 4 heccx_tx
6.16 ethernet media access controller (emac) 6.16.1 emac peripheral register description(s) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com the ethernet media access controller (emac) provides an efficient interface between dm6431 and the network. the dm6431 emac supports both 10base-t (10 mbits/second [mbps]) and 100base-tx (100 mbps) in either half- or full-duplex mode. the emac module also supports hardware flow control and quality of service (qos) support. the emac controls the flow of packet data from the dm6431 device to the phy. the mdio module controls phy configuration and status monitoring. the emac module conforms to the ieee 802.3-2002 standard, describing the ?carrier sense multiple access with collision detection (csma/cd) access method and physical layer? specifications. the ieee 802.3 standard has also been adopted by iso/iec and re-designated as iso/iec 8802-3:2000(e). deviation from this standard, the emac module does not use the transmit coding error signal mtxer. instead of driving the error pin when an underflow condition occurs on a transmitted frame, the emac will intentionally generate an incorrect checksum by inverting the frame crc, so that the transmitted frame will be detected as an error by the network. both the emac and the mdio modules interface to the dm6431 device through a custom interface that allows efficient data transmission and reception. this custom interface is referred to as the emac control module, and is considered integral to the emac/mdio peripheral. the control module is also used to multiplex and control interrupts. for the dm6431 ethernet media access controller (emac)/management data input/output (mdio) module user's guide (literature number spru941) which describes the dm6431 emac peripheral in detail, see section 2.9 , documentation support section . for a list of supported registers and register fields, see table 6-63 [ethernet mac (emac) control registers] and table 6-64 [emac statistics registers] in this data manual. table 6-63. ethernet mac (emac) control registers hex address range acronym register name 01c8 0000 txidver transmit identification and version register 01c8 0004 txcontrol transmit control register 01c8 0008 txteardown transmit teardown register 01c8 0010 rxidver receive identification and version register 01c8 0014 rxcontrol receive control register 01c8 0018 rxteardown receive teardown register 01c8 0080 txintstatraw transmit interrupt status (unmasked) register 01c8 0084 txintstatmasked transmit interrupt status (masked) register 01c8 0088 txintmaskset transmit interrupt mask set register 01c8 008c txintmaskclear transmit interrupt mask clear register 01c8 0090 macinvector mac input vector register 01c8 00a0 rxintstatraw receive interrupt status (unmasked) register 01c8 00a4 rxintstatmasked receive interrupt status (masked) register 01c8 00a8 rxintmaskset receive interrupt mask set register 01c8 00ac rxintmaskclear receive interrupt mask clear register 01c8 00b0 macintstatraw mac interrupt status (unmasked) register 01c8 00b4 macintstatmasked mac interrupt status (masked) register 01c8 00b8 macintmaskset mac interrupt mask set register 01c8 00bc macintmaskclear mac interrupt mask clear register 01c8 0100 rxmbpenable receive multicast/broadcast/promiscuous channel enable register 01c8 0104 rxunicastset receive unicast enable set register peripheral information and electrical specifications 202 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-63. ethernet mac (emac) control registers (continued) hex address range acronym register name 01c8 0108 rxunicastclear receive unicast clear register 01c8 010c rxmaxlen receive maximum length register 01c8 0110 rxbufferoffset receive buffer offset register 01c8 0114 rxfilterlowthresh receive filter low priority frame threshold register 01c8 0120 rx0flowthresh receive channel 0 flow control threshold register 01c8 0124 rx1flowthresh receive channel 1 flow control threshold register 01c8 0128 rx2flowthresh receive channel 2 flow control threshold register 01c8 012c rx3flowthresh receive channel 3 flow control threshold register 01c8 0130 rx4flowthresh receive channel 4 flow control threshold register 01c8 0134 rx5flowthresh receive channel 5 flow control threshold register 01c8 0138 rx6flowthresh receive channel 6 flow control threshold register 01c8 013c rx7flowthresh receive channel 7 flow control threshold register 01c8 0140 rx0freebuffer receive channel 0 free buffer count register 01c8 0144 rx1freebuffer receive channel 1 free buffer count register 01c8 0148 rx2freebuffer receive channel 2 free buffer count register 01c8 014c rx3freebuffer receive channel 3 free buffer count register 01c8 0150 rx4freebuffer receive channel 4 free buffer count register 01c8 0154 rx5freebuffer receive channel 5 free buffer count register 01c8 0158 rx6freebuffer receive channel 6 free buffer count register 01c8 015c rx7freebuffer receive channel 7 free buffer count register 01c8 0160 maccontrol mac control register 01c8 0164 macstatus mac status register 01c8 0168 emcontrol emulation control register 01c8 016c fifocontrol fifo control register (transmit and receive) 01c8 0170 macconfig mac configuration register 01c8 0174 softreset soft reset register 01c8 01d0 macsrcaddrlo mac source address low bytes register (lower 32-bits) 01c8 01d4 macsrcaddrhi mac source address high bytes register (upper 16-bits) 01c8 01d8 machash1 mac hash address register 1 01c8 01dc machash2 mac hash address register 2 01c8 01e0 bofftest back off test register 01c8 01e4 tpacetest transmit pacing algorithm test register 01c8 01e8 rxpause receive pause timer register 01c8 01ec txpause transmit pause timer register 01c8 0200 - 01c8 02fc (see table 6-64 ) emac statistics registers 01c8 0500 macaddrlo mac address low bytes register 01c8 0504 macaddrhi mac address high bytes register 01c8 0508 macindex mac index register 01c8 0600 tx0hdp transmit channel 0 dma head descriptor pointer register 01c8 0604 tx1hdp transmit channel 1 dma head descriptor pointer register 01c8 0608 tx2hdp transmit channel 2 dma head descriptor pointer register 01c8 060c tx3hdp transmit channel 3 dma head descriptor pointer register 01c8 0610 tx4hdp transmit channel 4 dma head descriptor pointer register 01c8 0614 tx5hdp transmit channel 5 dma head descriptor pointer register 01c8 0618 tx6hdp transmit channel 6 dma head descriptor pointer register 01c8 061c tx7hdp transmit channel 7 dma head descriptor pointer register 01c8 0620 rx0hdp receive channel 0 dma head descriptor pointer register submit documentation feedback peripheral information and electrical specifications 203
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-63. ethernet mac (emac) control registers (continued) hex address range acronym register name 01c8 0624 rx1hdp receive channel 1 dma head descriptor pointer register 01c8 0628 rx2hdp receive channel 2 dma head descriptor pointer register 01c8 062c rx3hdp receive channel 3 dma head descriptor pointer register 01c8 0630 rx4hdp receive channel 4 dma head descriptor pointer register 01c8 0634 rx5hdp receive channel 5 dma head descriptor pointer register 01c8 0638 rx6hdp receive channel 6 dma head descriptor pointer register 01c8 063c rx7hdp receive channel 7 dma head descriptor pointer register transmit channel 0 completion pointer (interrupt acknowledge) 01c8 0640 tx0cp register transmit channel 1 completion pointer (interrupt acknowledge) 01c8 0644 tx1cp register transmit channel 2 completion pointer (interrupt acknowledge) 01c8 0648 tx2cp register transmit channel 3 completion pointer (interrupt acknowledge) 01c8 064c tx3cp register transmit channel 4 completion pointer (interrupt acknowledge) 01c8 0650 tx4cp register transmit channel 5 completion pointer (interrupt acknowledge) 01c8 0654 tx5cp register transmit channel 6 completion pointer (interrupt acknowledge) 01c8 0658 tx6cp register transmit channel 7 completion pointer (interrupt acknowledge) 01c8 065c tx7cp register receive channel 0 completion pointer (interrupt acknowledge) 01c8 0660 rx0cp register receive channel 1 completion pointer (interrupt acknowledge) 01c8 0664 rx1cp register receive channel 2 completion pointer (interrupt acknowledge) 01c8 0668 rx2cp register receive channel 3 completion pointer (interrupt acknowledge) 01c8 066c rx3cp register receive channel 4 completion pointer (interrupt acknowledge) 01c8 0670 rx4cp register receive channel 5 completion pointer (interrupt acknowledge) 01c8 0674 rx5cp register receive channel 6 completion pointer (interrupt acknowledge) 01c8 0678 rx6cp register receive channel 7 completion pointer (interrupt acknowledge) 01c8 067c rx7cp register 204 peripheral information and electrical specifications submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-64. emac statistics registers hex address range acronym register name 01c8 0200 rxgoodframes good receive frames register broadcast receive frames register 01c8 0204 rxbcastframes (total number of good broadcast frames received) multicast receive frames register 01c8 0208 rxmcastframes (total number of good multicast frames received) 01c8 020c rxpauseframes pause receive frames register receive crc errors register (total number of frames received with 01c8 0210 rxcrcerrors crc errors) receive alignment/code errors register 01c8 0214 rxaligncodeerrors (total number of frames received with alignment/code errors) receive oversized frames register 01c8 0218 rxoversized (total number of oversized frames received) receive jabber frames register 01c8 021c rxjabber (total number of jabber frames received) receive undersized frames register 01c8 0220 rxundersized (total number of undersized frames received) 01c8 0224 rxfragments receive frame fragments register 01c8 0228 rxfiltered filtered receive frames register 01c8 022c rxqosfiltered received qos filtered frames register receive octet frames register 01c8 0230 rxoctets (total number of received bytes in good frames) good transmit frames register 01c8 0234 txgoodframes (total number of good frames transmitted) 01c8 0238 txbcastframes broadcast transmit frames register 01c8 023c txmcastframes multicast transmit frames register 01c8 0240 txpauseframes pause transmit frames register 01c8 0244 txdeferred deferred transmit frames register 01c8 0248 txcollision transmit collision frames register 01c8 024c txsinglecoll transmit single collision frames register 01c8 0250 txmulticoll transmit multiple collision frames register 01c8 0254 txexcessivecoll transmit excessive collision frames register 01c8 0258 txlatecoll transmit late collision frames register 01c8 025c txunderrun transmit underrun error register 01c8 0260 txcarriersense transmit carrier sense errors register 01c8 0264 txoctets transmit octet frames register 01c8 0268 frame64 transmit and receive 64 octet frames register 01c8 026c frame65t127 transmit and receive 65 to 127 octet frames register 01c8 0270 frame128t255 transmit and receive 128 to 255 octet frames register 01c8 0274 frame256t511 transmit and receive 256 to 511 octet frames register 01c8 0278 frame512t1023 transmit and receive 512 to 1023 octet frames register 01c8 027c frame1024tup transmit and receive 1024 to 1518 octet frames register 01c8 0280 netoctets network octet frames register 01c8 0284 rxsofoverruns receive fifo or dma start of frame overruns register 01c8 0288 rxmofoverruns receive fifo or dma middle of frame overruns register receive dma start of frame and middle of frame overruns 01c8 028c rxdmaoverruns register submit documentation feedback peripheral information and electrical specifications 205
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-65. emac control module registers hex address range acronym register name 0x01c8 1004 ewctl interrupt control register 0x01c8 1008 ewinttcnt interrupt timer count table 6-66. emac control module ram hex address range acronym register name 0x01c8 2000 - 0x01c8 3fff emac control module descriptor memory peripheral information and electrical specifications 206 submit documentation feedback
6.16.2 emac electrical data/timing tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-67. timing requirements for mrclk (see figure 6-37 ) -3/-3q/-3s no. 10 mbps 100 mbps unit min max min max 1 t c(mrclk) cycle time, mrclk 400 40 ns 2 t w(mrclkh) pulse duration, mrclk high 140 14 ns 3 t w(mrclkl) pulse duration, mrclk low 140 14 ns figure 6-37. mrclk timing (emac - receive) table 6-68. timing requirements for mtclk (see figure 6-37 ) -3/-3q/-3s no. 10 mbps 100 mbps unit min max min max 1 t c(mtclk) cycle time, mtclk 400 40 ns 2 t w(mtclkh) pulse duration, mtclk high 140 14 ns 3 t w(mtclkl) pulse duration, mtclk low 140 14 ns figure 6-38. mtclk timing (emac - transmit) table 6-69. timing requirements for emac mii receive 10/100 mbit/s (1) (see figure 6-39 ) -3/-3q/-3s no. unit min max 1 t su(mrxd-mrclkh) setup time, receive selected signals valid before mrclk high 8 ns 2 t h(mrclkh-mrxd) hold time, receive selected signals valid after mrclk high 8 ns (1) receive selected signals include: mrxd3-mrxd0, mrxdv, and mrxer. figure 6-39. emac receive interface timing submit documentation feedback peripheral information and electrical specifications 207 mrclk 2 3 1 mtclk 2 3 1 mrclk (input) 1 2 mrxd3?mrxd0, mrxdv , mrxer (inputs)
tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-70. switching characteristics over recommended operating conditions for emac mii transmit 10/100 mbit/s (1) (see figure 6-40 ) -3/-3q/-3s no. unit min max 1 t d(mtclkh-mtxd) delay time, mtclk high to transmit selected signals valid 2 25 ns (1) transmit selected signals include: mtxd3-mtxd0, and mtxen. figure 6-40. emac transmit interface timing 208 peripheral information and electrical specifications submit documentation feedback 1 mtclk (input) mtxd3?mtxd0, mtxen (outputs)
6.17 management data input/output (mdio) 6.17.1 peripheral register description(s) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the management data input/output (mdio) module continuously polls all 32 mdio addresses in order to enumerate all phy devices in the system. the management data input/output (mdio) module implements the 802.3 serial management interface to interrogate and control ethernet phy(s) using a shared two-wire bus. host software uses the mdio module to configure the auto-negotiation parameters of each phy attached to the emac, retrieve the negotiation results, and configure required parameters in the emac module for correct operation. the module is designed to allow almost transparent operation of the mdio interface, with very little maintenance from the core processor. only one phy may be connected at any given time. for more detailed information on the mdio peripheral, see the documentation support section for the ethernet media access controller (emac)/management data input/output (mdio) module reference guide. for a list of supported registers and register fields, see table 6-71 [mdio registers] in this data manual. table 6-71. mdio registers hex address range acronym register name 0x01c8 4000 ? reserved 0x01c8 4004 control mdio control register 0x01c8 4008 alive mdio phy alive status register 0x01c8 400c link mdio phy link status register 0x01c8 4010 linkintraw mdio link status change interrupt (unmasked) register 0x01c8 4014 linkintmasked mdio link status change interrupt (masked) register 0x01c8 4018 ? reserved 0x01c8 4020 userintraw mdio user command complete interrupt (unmasked) register 0x01c8 4024 userintmasked mdio user command complete interrupt (masked) register 0x01c8 4028 userintmaskset mdio user command complete interrupt mask set register 0x01c8 402c userintmaskclear mdio user command complete interrupt mask clear register 0x01c8 4030 - 0x01c8 407c ? reserved 0x01c8 4080 useraccess0 mdio user access register 0 0x01c8 4084 userphysel0 mdio user phy select register 0 0x01c8 4088 useraccess1 mdio user access register 1 0x01c8 408c userphysel1 mdio user phy select register 1 0x01c8 4090 - 0x01c8 47ff ? reserved submit documentation feedback peripheral information and electrical specifications 209
6.17.2 management data input/output (mdio) electrical data/timing 6.18 timers tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-72. timing requirements for mdio input (see figure 6-41 and figure 6-42 ) -3/-3q/-3s no. unit min max 1 t c(mdclk) cycle time, mdclk 400 ns 2 t w(mdclk) pulse duration, mdclk high/low 180 ns 3 t t(mdclk) transition time, mdclk 5 ns 4 t su(mdio-mdclkh) setup time, mdio data input valid before mdclk high 10 ns 5 t h(mdclkh-mdio) hold time, mdio data input valid after mdclk high 10 ns figure 6-41. mdio input timing table 6-73. switching characteristics over recommended operating conditions for mdio output (see figure 6-42 ) -3/-3q/-3s no. unit min max 7 t d(mdclkl-mdio) delay time, mdclk low to mdio data output valid 100 ns figure 6-42. mdio output timing the dm6431 device has 3 64-bit general-purpose timers which have the following features: 64-bit count-up counter timer modes: ? 64-bit general-purpose timer mode (timer 0 and 1) ? dual 32-bit general-purpose timer mode (timer 0 and 1) ? watchdog timer mode (timer 2) 2 possible clock sources: ? internal clock peripheral information and electrical specifications 210 submit documentation feedback 1 4 5 mdclk mdio (input) 3 3 1 7 mdclk mdio (output)
6.18.1 timer peripheral register description(s) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 ? external clock input via timer input pin tinpl (timer 0 and 1 only) 2 operation modes: ? one-time operation (timer runs for one period then stops) ? continuous operation (timer automatically resets after each period) generates interrupts to the dsp generates sync event to edma causes device global reset upon watchdog timer timeout (timer 2 only) for more detailed information, see section 2.9 , documentation support for the tms320dm643x dmp 64-bit timer user's guide (literature number spru989). table 6-74. timer 0 registers hex address range acronym description 0x01c2 1400 - reserved 0x01c2 1404 emumgt_clkspd timer 0 emulation management/clock speed register 0x01c2 1410 tim12 timer 0 counter register 12 0x01c2 1414 tim34 timer 0 counter register 34 0x01c2 1418 prd12 timer 0 period register 12 0x01c2 141c prd34 timer 0 period register 34 0x01c2 1420 tcr timer 0 control register 0x01c2 1424 tgcr timer 0 global control register 0x01c2 1428 - 0x01c2 17ff - reserved table 6-75. timer 1 registers hex address range acronym description 0x01c2 1800 - reserved 0x01c2 1804 emumgt_clkspd timer 1 emulation management/clock speed register 0x01c2 1810 tim12 timer 1 counter register 12 0x01c2 1814 tim34 timer 1 counter register 34 0x01c2 1818 prd12 timer 1 period register 12 0x01c2 181c prd34 timer 1 period register 34 0x01c2 1820 tcr timer 1 control register 0x01c2 1824 tgcr timer 1 global control register 0x01c2 1828 - 0x01c2 1bff - reserved table 6-76. timer 2 (watchdog) registers hex address range acronym description 0x01c2 1c00 - reserved 0x01c2 1c04 emumgt_clkspd timer 2 emulation management/clock speed register 0x01c2 1c10 tim12 timer 2 counter register 12 0x01c2 1c14 tim34 timer 2 counter register 34 0x01c2 1c18 prd12 timer 2 period register 12 0x01c2 1c1c prd34 timer 2 period register 34 0x01c2 1c20 tcr timer 2 control register 0x01c2 1c24 tgcr timer 2 global control register 0x01c2 1c28 wdtcr timer 2 watchdog timer control register 0x01c2 1c2c - 0x01c2 1fff - reserved submit documentation feedback peripheral information and electrical specifications 211
6.18.2 timer electrical data/timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-77. timing requirements for timer input (1) (2) (3) (see figure 6-43 ) -3/-3q/-3s no. unit min max tinp0l, if timerctl.tinp0sel = 0 2p ns [default] 1 t w(tinph) pulse duration, tinpxl high tinp0l, if timerctl.tinp0sel = 1 0.33p ns tinp1l 2p ns tinp0l, if timerctl.tinp0sel = 0 2p ns [default] 2 t w(tinpl) pulse duration, tinpxl low tinp0l, if timerctl.tinp0sel = 1 0.33p ns tinp1l 2p ns (1) p = mxi/clkin cycle time in ns. for example, when mxi/clkin frequency is 27 mhz, use p = 37.0 37 ns. (2) the timerctl.tinp0sel field in the system module determines if the tinp0l input directly goes to timer 0 (timerctl.tinp0sel=0), or if the tinp0l input is first divided down by 6 before going to timer 0 (timerctl.tinp0sel=1). (3) tinp1l input goes directly to timer 1. table 6-78. switching characteristics over recommended operating conditions for timer output (1) (see figure 6-43 ) -3/-3q/-3s no. unit min max 3 t w(touth) pulse duration, toutxl high p ns 4 t w(toutl) pulse duration, toutxl low p ns (1) p = mxi/clkin cycle time in ns. for example, when mxi/clkin frequency is 27 mhz, use p = 37.0 37 ns. figure 6-43. timer timing 212 peripheral information and electrical specifications submit documentation feedback tinpxl toutxl 1 2 3 4
6.19 pulse width modulator (pwm) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the 3 dm6431 pulse width modulator (pwm) peripherals support the following features: period counter first-phase duration counter repeat count for one-shot operation configurable to operate in either one-shot or continuous mode buffered period and first-phase duration registers one-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or high-to-low). one-shot operation generates n+1 periods of waveform, n being the repeat count register value emulation support the register memory maps for pwm0/1/2 are shown in table 6-79 , table 6-80 , and table 6-81 . table 6-79. pwm0 register memory map hex address range acronym register name 0x01c2 2000 reserved 0x01c2 2004 pcr pwm0 peripheral control register 0x01c2 2008 cfg pwm0 configuration register 0x01c2 200c start pwm0 start register 0x01c2 2010 rpt pwm0 repeat count register 0x01c2 2014 per pwm0 period register 0x01c2 2018 ph1d pwm0 first-phase duration register 0x01c2 201c - 0x01c2 23ff - reserved table 6-80. pwm1 register memory map hex address range acronym register name 0x01c2 2400 reserved 0x01c2 2404 pcr pwm1 peripheral control register 0x01c2 2408 cfg pwm1 configuration register 0x01c2 240c start pwm1 start register 0x01c2 2410 rpt pwm1 repeat count register 0x01c2 2414 per pwm1 period register 0x01c2 2418 ph1d pwm1 first-phase duration register 0x01c2 241c -0x01c2 27ff - reserved table 6-81. pwm2 register memory map hex address range acronym register name 0x01c2 2800 reserved 0x01c2 2804 pcr pwm2 peripheral control register 0x01c2 2808 cfg pwm2 configuration register 0x01c2 280c start pwm2 start register 0x01c2 2810 rpt pwm2 repeat count register 0x01c2 2814 per pwm2 period register 0x01c2 2818 ph1d pwm2 first-phase duration register 0x01c2 281c - 0x01c2 2bff - reserved submit documentation feedback peripheral information and electrical specifications 213
6.19.1 pwm0/1/2 electrical data/timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-82. switching characteristics over recommended operating conditions for pwm0/1/2 outputs (see figure 6-44 and figure 6-45 ) -3/-3q/-3s no. parameter unit min max 1 t w(pwmh) pulse duration, pwmx high 37 ns 2 t w(pwml) pulse duration, pwmx low 37 ns 3 t t(pwm) transition time, pwmx 5 ns 4 t d(ccdc-pwmv) delay time, ccdc(vd) trigger event to pwmx valid 2 10 ns figure 6-44. pwm output timing figure 6-45. pwm output delay timing 214 peripheral information and electrical specifications submit documentation feedback pwm0/1/2 1 3 3 2 4 vd(ccdc) 4 4 invalid invalid invalid valid valid valid pwm0pwm1 pwm2
6.20 general-purpose input/output (gpio) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the gpio peripheral provides general-purpose pins that can be configured as either inputs or outputs. when configured as an output, a write to an internal register can control the state driven on the output pin. when configured as an input, the state of the input is detectable by reading the state of an internal register. in addition, the gpio peripheral can produce cpu interrupts and edma events in different interrupt/event generation modes. the gpio peripheral provides generic connections to external devices. the gpio pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of gp[0:15]). the dm6431 gpio peripheral supports the following: up to 111 3.3-v gpio pins, gp[0:110] interrupts: ? up to 8 unique gp[0:7] interrupts from bank 0 ? 7 gpio bank (aggregated) interrupt signals from each of the 7 banks of gpios ? interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable gpio signal dma events: ? up to 8 unique gpio dma events from bank 0 ? 7 gpio bank (aggregated) dma event signals from each of the 7 banks of gpios set/clear functionality: firmware writes 1 to corresponding bit position(s) to set or to clear gpio signal(s). this allows multiple firmware processes to toggle gpio output signals without critical section protection (disable interrupts, program gpio, re-enable interrupts, to prevent context switching to anther process during gpio programming). separate input/output registers output register in addition to set/clear so that, if preferred by firmware, some gpio output signals can be toggled by direct write to the output register(s). output register, when read, reflects output drive status. this, in addition to the input register reflecting pin status and open-drain i/o cell, allows wired logic be implemented. the memory map for the gpio registers is shown in table 6-83 . for more detailed information on gpios, see the tms320dm643x dmp general-purpose input/output (gpio) user's guide (literature number spru988 ). submit documentation feedback peripheral information and electrical specifications 215
6.20.1 gpio peripheral register description(s) tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-83. gpio registers hex address range acronym register name 0x01c6 7000 pid peripheral identification register 0x01c6 7004 - reserved 0x01c6 7008 binten gpio interrupt per-bank enable gpio banks 0 and 1 0x01c6 700c - reserved 0x01c6 7010 dir01 gpio banks 0 and 1 direction register (gp[0:31]) 0x01c6 7014 out_data01 gpio banks 0 and 1 output data register (gp[0:31]) 0x01c6 7018 set_data01 gpio banks 0 and 1 set data register (gp[0:31]) 0x01c6 701c clr_data01 gpio banks 0 and 1 clear data for banks 0 and 1 (gp[0:31]) 0x01c6 7020 in_data01 gpio banks 0 and 1 input data register (gp[0:31]) 0x01c6 7024 set_ris_trig01 gpio banks 0 and 1 set rising edge interrupt register (gp[0:31]) 0x01c6 7028 clr_ris_trig01 gpio banks 0 and 1 clear rising edge interrupt register (gp[0:31]) 0x01c6 702c set_fal_trig01 gpio banks 0 and 1 set falling edge interrupt register (gp[0:31]) 0x01c6 7030 clr_fal_trig01 gpio banks 0 and 1 clear falling edge interrupt register (gp[0:31]) 0x01c6 7034 instat01 gpio banks 0 and 1 interrupt status register (gp[0:31]) gpio banks 2 and 3 0x01c6 7038 dir23 gpio banks 2 and 3 direction register (gp[32:63]) 0x01c6 703c out_data23 gpio banks 2 and 3 output data register (gp[32:63]) 0x01c6 7040 set_data23 gpio banks 2 and 3 set data register (gp[32:63]) 0x01c6 7044 clr_data23 gpio banks 2 and 3 clear data register (gp[32:63]) 0x01c6 7048 in_data23 gpio banks 2 and 3 input data register (gp[32:63]) 0x01c6 704c set_ris_trig23 gpio banks 2 and 3 set rising edge interrupt register (gp[32:63]) 0x01c6 7050 clr_ris_trig23 gpio banks 2 and 3 clear rising edge interrupt register (gp[32:63]) 0x01c6 7054 set_fal_trig23 gpio banks 2 and 3 set falling edge interrupt register (gp[32:63]) 0x01c6 7058 clr_fal_trig23 gpio banks 2 and 3 clear falling edge interrupt register (gp[32:63]) 0x01c6 705c instat23 gpio banks 2 and 3 interrupt status register (gp[32:63]) gpio bank 4 and 5 0x01c6 7060 dir45 gpio bank 4 and 5 direction register (gp[64:95]) 0x01c6 7064 out_data45 gpio bank 4 and 5 output data register (gp[64:95]) 0x01c6 7068 set_data45 gpio bank 4 and 5 set data register (gp[64:95]) 0x01c6 706c clr_data45 gpio bank 4 and 5 clear data register (gp[64:95]) 0x01c6 7070 in_data45 gpio bank 4 and 5 input data register (gp[64:95]) 0x01c6 7074 set_ris_trig45 gpio bank 4 and 5 set rising edge interrupt register (gp[64:95]) 0x01c6 7078 clr_ris_trig45 gpio bank 4 and 5 clear rising edge interrupt register (gp[64:95]) 0x01c6 707c set_fal_trig45 gpio bank 4 and 5 set falling edge interrupt register (gp[64:95]) 0x01c6 7080 clr_fal_trig45 gpio bank 4 and 5 clear falling edge interrupt register (gp[64:95]) 0x01c6 7084 instat45 gpio bank 4 and 5 interrupt status register (gp[64:95]) gpio bank 6 0x01c6 7088 dir6 gpio bank 6 direction register (gp[96:110]) 0x01c6 708c out_data6 gpio bank 6 output data register (gp[96:110]) 0x01c6 7090 set_data6 gpio bank 6 set data register (gp[96:110]) 0x01c6 7094 clr_data6 gpio bank 6 clear data register (gp[96:110]) 0x01c6 7098 in_data6 gpio bank 6 input data register (gp[96:110]) 0x01c6 709c set_ris_trig6 gpio bank 6 set rising edge interrupt register (gp[96:110]) 0x01c6 70a0 clr_ris_trig6 gpio bank 6 clear rising edge interrupt register (gp[96:110]) peripheral information and electrical specifications 216 submit documentation feedback
tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 table 6-83. gpio registers (continued) hex address range acronym register name 0x01c6 70a4 set_fal_trig6 gpio bank 6 set falling edge interrupt register (gp[96:110]) 0x01c6 70a8 clr_fal_trig6 gpio bank 6 clear falling edge interrupt register (gp[96:110]) 0x01c6 70ac instat6 gpio bank 6 interrupt status register (gp[96:110]) 0x01c6 70b0 - 0x01c6 7fff - reserved submit documentation feedback peripheral information and electrical specifications 217
6.20.2 gpio peripheral input/output electrical data/timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-84. timing requirements for gpio inputs (1) (see figure 6-46 ) -3/-3q/-3s no. unit min max 1 t w(gpih) pulse duration, gp[x] input high 2c (2) ns 2 t w(gpil) pulse duration, gp[x] input low 2c (2) ns (1) the pulse width given is sufficient to generate a cpu interrupt or an edma event. however, if a user wants to have dm6431 recognize the gp[x] input changes through software polling of the gpio register, the gp[x] input duration must be extended to allow dm6431 enough time to access the gpio register through the internal bus. (2) c = sysclk3 period in ns. for example, when running parts at 300 mhz, use c = 20 ns. table 6-85. switching characteristics over recommended operating conditions for gpio outputs (see figure 6-46 ) -3/-3q/-3s no. parameter unit min max 3 t w(gpoh) pulse duration, gp[x] output high 2c (1) (2) ns 4 t w(gpol) pulse duration, gp[x] output low 2c (1) (2) ns (1) this parameter value should not be used as a maximum performance specification. actual performance of back-to-back accesses of the gpio is dependent upon internal bus activity. (2) c = sysclk3 period in ns. for example, when running parts at 300 mhz, use c = 20 ns. figure 6-46. gpio port timing 218 peripheral information and electrical specifications submit documentation feedback gp[x] input gp[x] output 4 3 2 1
6.21 ieee 1149.1 jtag 6.21.1 jtag id (jtagid) register description(s) tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the jtag (3) interface is used for bsdl testing and emulation of the dm6431 device. trst only needs to be released when it is necessary to use a jtag controller to debug the device or exercise the device's boundary scan functionality. note: trst is synchronous and must be clocked by tck; otherwise, the boundary scan logic may not respond as expected after trst is asserted. for maximum reliability, dm6431 includes an internal pulldown (ipd) on the trst pin to ensure that trst will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. jtag controllers from texas instruments actively drive trst high. however, some third-party jtag controllers may not drive trst high but expect the use of a pullup resistor on trst. when using this type of jtag controller, assert trst to initialize the device after powerup and externally drive trst high before attempting any emulation or boundary scan operations. (3) ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. table 6-86. jtag id (jtagid) register hex address range acronym register name comments read-only. provides 32-bit 0x01c4 0028 jtagid jtag identification register jtag id of the device. the jtag id register is a read-only register that identifies to the customer the jtag/device id. for the dm6431 device, the jtag id register resides at address location 0x01c4 0028. for the actual register bit names and their associated bit field descriptions, see figure 6-47 and table 6-87 . 31-28 27-12 11-1 0 variant (4-bit) part number (16-bit) manufacturer (11-bit) lsb r-n r-1011 0111 0010 0001 r-0000 0010 111 r-1 legend: r = read, w = write, n = value at reset figure 6-47. jtag id (jtagid) register?0x01c4 0028 table 6-87. jtag id (jtagid) register selection bit descriptions bit name description 31:28 variant variant (4-bit) value. a read from this field always returns 0b0000. 27:12 part number part number (16-bit) value. dm6431 value: 1011 0111 0010 0001. 11-1 manufacturer manufacturer (11-bit) value. dm6431 value: 0000 0010 111. 0 lsb lsb. this bit is read as a "1" for dm6431. submit documentation feedback peripheral information and electrical specifications 219
6.21.2 jtag electrical data/timing tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 6-88. timing requirements for jtag test port (see figure 6-48 ) -3/-3q/-3s no. unit min max 1 t c(tck) cycle time, tck 33 ns 3 t su(tdiv-tckh) setup time, tdi/tms/ trst valid before tck high 2.5 ns 4 t h(tckh-tdiv) hold time, tdi/tms/ trst valid after tck high 16.5 ns table 6-89. switching characteristics over recommended operating conditions for jtag test port (see figure 6-48 ) -3/-3q/-3s no. parameter unit min max 2 t d(tckl-tdov) delay time, tck low to tdo valid 0 14 ns figure 6-48. jtag test-port timing peripheral information and electrical specifications 220 submit documentation feedback tck tdo tdi/tms/trst 1 2 3 4 2
7 mechanical data 7.1 thermal data for zwt tms320dm6431 digital media processor www.ti.com sprs342c ? november 2006 ? revised june 2008 the following table(s) show the thermal resistance characteristics for the pbga?zwt and zdu mechanical package(s). for more details, see the thermal considerations for tms320dm64xx, tms320dm64x, and tms320c6000 devices application report (literature number spraal9 ). table 7-1. thermal resistance characteristics (pbga package) [zwt] no. c/w (1) air flow (m/s) (2) 1 r integrated circuits thermal test method environment conditions - natural convection (still air) eia/jesd51-3, low effective thermal conductivity test board for leaded surface mount packages jesd51-7, high effective thermal conductivity test board for leaded surface mount packages . (2) m/s = meters per second submit documentation feedback mechanical data 221
7.1.1 thermal data for zdu 7.1.2 packaging information tms320dm6431 digital media processor sprs342c ? november 2006 ? revised june 2008 www.ti.com table 7-2. thermal resistance characteristics (pbga package) [zdu] no. c/w (1) air flow (m/s) (2) 1 r integrated circuits thermal test method environment conditions - natural convection (still air) eia/jesd51-3, low effective thermal conductivity test board for leaded surface mount packages jesd51-7, high effective thermal conductivity test board for leaded surface mount packages (2) m/s = meters per second the following packaging information and addendum reflect the most current data available for the designated device(s). this data is subject to change without notice and without revision of this document. 222 mechanical data submit documentation feedback
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TMS320DM6431ZDU3 nrnd bga zdu 376 60 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 l2 dm6431zdu tms320 3 tms320dm6431zwt3 nrnd nfbga zwt 361 90 pb-free (rohs) snagcu level-3-260c-168 hr 0 to 90 l2 dm6431zwt tms320 3 tms320dm6431zwtq3 active nfbga zwt 361 90 pb-free (rohs) snagcu level-3-260c-168 hr -40 to 125 l1 dm6431zwtq tms320 3 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 15-apr-2017 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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